From mboxrd@z Thu Jan 1 00:00:00 1970 From: shuang.he@intel.com Subject: Re: [PATCH] drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL Date: 05 Feb 2015 11:41:16 -0800 Message-ID: <71e320$fivk8h@orsmga003.jf.intel.com> References: <1423136325-16532-1-git-send-email-shobhit.kumar@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 7070E6E867 for ; Thu, 5 Feb 2015 11:49:03 -0800 (PST) In-Reply-To: <1423136325-16532-1-git-send-email-shobhit.kumar@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: shuang.he@intel.com, ethan.gao@intel.com, intel-gfx@lists.freedesktop.org, shobhit.kumar@intel.com List-Id: intel-gfx@lists.freedesktop.org VGVzdGVkLUJ5OiBQUkMgUUEgUFJUUyAoUGF0Y2ggUmVncmVzc2lvbiBUZXN0IFN5c3RlbSBDb250 YWN0OiBzaHVhbmcuaGVAaW50ZWwuY29tKQpUYXNrIGlkOiA1NzE4Ci0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS1TdW1tYXJ5LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLQpQbGF0Zm9ybSAgICAgICAgICBEZWx0YSAgICAgICAgICBkcm0taW50ZWwtbmlnaHRs eSAgICAgICAgICBTZXJpZXMgQXBwbGllZApQTlYgICAgICAgICAgICAgICAgIC04ICAgICAgICAg ICAgICAyODIvMjgzICAgICAgICAgICAgICAyNzQvMjgzCklMSyAgICAgICAgICAgICAgKzEgICAg ICAgICAgICAgICAgIDMxNi8zMTkgICAgICAgICAgICAgIDMxNy8zMTkKU05CICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgIDMyMi8zNDYgICAgICAgICAgICAgIDMyMi8zNDYKSVZCICAg ICAgICAgICAgICAgICAtMSAgICAgICAgICAgICAgMzgyLzM4NCAgICAgICAgICAgICAgMzgxLzM4 NApCWVQgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgMjk2LzI5NiAgICAgICAgICAg ICAgMjk2LzI5NgpIU1cgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgNDI1LzQyOCAg ICAgICAgICAgICAgNDI1LzQyOApCRFcgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg MzE4LzMzMyAgICAgICAgICAgICAgMzE4LzMzMwotLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tRGV0YWlsZWQtLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tClBs YXRmb3JtICBUZXN0ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBkcm0taW50ZWwtbmln aHRseSAgICAgICAgICBTZXJpZXMgQXBwbGllZAoqUE5WICBpZ3RfZ2VtX2ZlbmNlX3RocmFzaF9i by13cml0ZS12ZXJpZnkteSAgICAgIFBBU1MoMiwgTTIzTTcpICAgICAgRkFJTCgxLCBNNykKIFBO ViAgaWd0X2dlbV91c2VycHRyX2JsaXRzX2NvaGVyZW5jeS1zeW5jICAgICAgQ1JBU0goMiwgTTcp UEFTUygxLCBNMjMpICAgICAgQ1JBU0goMSwgTTcpCiBQTlYgIGlndF9nZW1fdXNlcnB0cl9ibGl0 c19jb2hlcmVuY3ktdW5zeW5jICAgICAgQ1JBU0goMiwgTTcpUEFTUygxLCBNMjMpICAgICAgQ1JB U0goMSwgTTcpCipQTlYgIGlndF9nZW1fdXNlcnB0cl9ibGl0c19mb3JrZWQtc3luYy1pbnRlcnJ1 cHRpYmxlICAgICAgUEFTUygyLCBNMjNNNykgICAgICBETUVTR19XQVJOKDEsIE03KQoqUE5WICBp Z3RfZ2VtX3VzZXJwdHJfYmxpdHNfZm9ya2VkLXN5bmMtbXVsdGlmZC1pbnRlcnJ1cHRpYmxlICAg ICAgUEFTUygyLCBNMjNNNykgICAgICBOT19SRVNVTFQoMSwgTTcpCiBQTlYgIGlndF9nZW4zX3Jl bmRlcl9saW5lYXJfYmxpdHMgICAgICBGQUlMKDMsIE03KUNSQVNIKDEsIE0yMylQQVNTKDQsIE0y NU0yMykgICAgICBGQUlMKDEsIE03KQogUE5WICBpZ3RfZ2VuM19yZW5kZXJfbWl4ZWRfYmxpdHMg ICAgICBGQUlMKDMsIE03KVBBU1MoMSwgTTIzKSAgICAgIEZBSUwoMSwgTTcpCiBQTlYgIGlndF9n ZW4zX3JlbmRlcl90aWxlZHhfYmxpdHMgICAgICBGQUlMKDIsIE03KVBBU1MoMSwgTTIzKSAgICAg IEZBSUwoMSwgTTcpCiBQTlYgIGlndF9nZW1fdGlsZWRfcHJlYWRfcHdyaXRlICAgICAgRkFJTCgy LCBNNylQQVNTKDEsIE0yMykgICAgICBGQUlMKDEsIE03KQoqSUxLICBpZ3RfZHJ2X3N1c3BlbmRf Zm9yY2V3YWtlICAgICAgRE1FU0dfV0FSTig1LCBNMjZNMzcpICAgICAgUEFTUygxLCBNMjYpCiBJ VkIgIGlndF9nZW1fcHdyaXRlX3ByZWFkX3Nub29wZWQtcHdyaXRlLWJsdC1jcHVfbW1hcC1wZXJm b3JtYW5jZSAgICAgIERNRVNHX1dBUk4oMiwgTTM0KVBBU1MoNSwgTTIxTTM0KSAgICAgIERNRVNH X1dBUk4oMSwgTTIxKQpOb3RlOiBZb3UgbmVlZCB0byBwYXkgbW9yZSBhdHRlbnRpb24gdG8gbGlu ZSBzdGFydCB3aXRoICcqJwpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fXwpJbnRlbC1nZnggbWFpbGluZyBsaXN0CkludGVsLWdmeEBsaXN0cy5mcmVlZGVza3Rv cC5vcmcKaHR0cDovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVs LWdmeAo=