From mboxrd@z Thu Jan 1 00:00:00 1970 From: Lionel Landwerlin Subject: Re: [Intel-gfx] [PATCH 02/25] drm/i915: Mark pin flags as u64 Date: Fri, 2 Nov 2018 16:48:07 +0000 Message-ID: <720e06d9-113a-52ab-d1c5-8556c51b9258@intel.com> References: <20181102161232.17742-1-chris@chris-wilson.co.uk> <20181102161232.17742-2-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20181102161232.17742-2-chris@chris-wilson.co.uk> Content-Language: en-US Sender: stable-owner@vger.kernel.org To: Chris Wilson , intel-gfx@lists.freedesktop.org Cc: stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On 02/11/2018 16:12, Chris Wilson wrote: > Since the flags are being used to operate on a u64 variable, they too > need to be marked as such so that the inverses are full width (and not > zero extended on 32b kernels and bdw+). > > Reported-by: Sergii Romantsov > Signed-off-by: Chris Wilson > Cc: stable@vger.kernel.org Feels like Sergii should have done a v2. Reviewed-by: Lionel Landwerlin > --- > drivers/gpu/drm/i915/i915_gem_gtt.h | 28 ++++++++++++++-------------- > 1 file changed, 14 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h > index a030299b79cd..4874da09a3c4 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h > @@ -660,20 +660,20 @@ int i915_gem_gtt_insert(struct i915_address_space *vm, > u64 start, u64 end, unsigned int flags); > > /* Flags used by pin/bind&friends. */ > -#define PIN_NONBLOCK BIT(0) > -#define PIN_MAPPABLE BIT(1) > -#define PIN_ZONE_4G BIT(2) > -#define PIN_NONFAULT BIT(3) > -#define PIN_NOEVICT BIT(4) > - > -#define PIN_MBZ BIT(5) /* I915_VMA_PIN_OVERFLOW */ > -#define PIN_GLOBAL BIT(6) /* I915_VMA_GLOBAL_BIND */ > -#define PIN_USER BIT(7) /* I915_VMA_LOCAL_BIND */ > -#define PIN_UPDATE BIT(8) > - > -#define PIN_HIGH BIT(9) > -#define PIN_OFFSET_BIAS BIT(10) > -#define PIN_OFFSET_FIXED BIT(11) > +#define PIN_NONBLOCK BIT_ULL(0) > +#define PIN_MAPPABLE BIT_ULL(1) > +#define PIN_ZONE_4G BIT_ULL(2) > +#define PIN_NONFAULT BIT_ULL(3) > +#define PIN_NOEVICT BIT_ULL(4) > + > +#define PIN_MBZ BIT_ULL(5) /* I915_VMA_PIN_OVERFLOW */ > +#define PIN_GLOBAL BIT_ULL(6) /* I915_VMA_GLOBAL_BIND */ > +#define PIN_USER BIT_ULL(7) /* I915_VMA_LOCAL_BIND */ > +#define PIN_UPDATE BIT_ULL(8) > + > +#define PIN_HIGH BIT_ULL(9) > +#define PIN_OFFSET_BIAS BIT_ULL(10) > +#define PIN_OFFSET_FIXED BIT_ULL(11) > #define PIN_OFFSET_MASK (-I915_GTT_PAGE_SIZE) > > #endif