[PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC

[PATCH v3 0/2] drm/i915/display: Enable system cache support for FBC

[Vinod Govindapillai]

Use system cacheability configuration register to assign a reserved
area in system cache for FBC

Vinod Govindapillai (2):
  drm/i915/display: Use a sub-struct for fbc operations in intel_display
  drm/i915/xe3p_lpd: Enable display use of system cache for FBC

 drivers/gpu/drm/i915/display/i9xx_plane.c     |  2 +-
 .../gpu/drm/i915/display/intel_display_core.h |  8 +-
 .../drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c      | 99 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
 .../drm/i915/display/skl_universal_plane.c    |  2 +-
 6 files changed, 116 insertions(+), 6 deletions(-)

-- 
2.43.0

[PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display

[Vinod Govindapillai]

As FBC can utilze the system cache in xe3p_lpd onwards, we need
a way to track which fbc instance is utilizing this cache. So we
would need to extend the intel_display with such a functionality.
Introduce a new fbc substruct and move the current fbc instance
array into that. Then the following patch can utilize this to
introduce functionaity to configure and track the system cache
usage by the fbc instance.

Suggested-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_plane.c          | 2 +-
 drivers/gpu/drm/i915/display/intel_display_core.h  | 5 ++++-
 drivers/gpu/drm/i915/display/intel_fbc.c           | 6 +++---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
 4 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index 51ccc6bd5f21..2c40bc632b3d 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -134,7 +134,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,
 					enum i9xx_plane_id i9xx_plane)
 {
 	if (i9xx_plane_has_fbc(display, i9xx_plane))
-		return display->fbc[INTEL_FBC_A];
+		return display->fbc.instances[INTEL_FBC_A];
 	else
 		return NULL;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 9b36654b593d..58325f530670 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -398,6 +398,10 @@ struct intel_display {
 		const struct dram_info *info;
 	} dram;
 
+	struct {
+		struct intel_fbc *instances[I915_MAX_FBCS];
+	} fbc;
+
 	struct {
 		/* list of fbdev register on this device */
 		struct intel_fbdev *fbdev;
@@ -615,7 +619,6 @@ struct intel_display {
 	struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
 	struct intel_audio audio;
 	struct intel_dpll_global dpll;
-	struct intel_fbc *fbc[I915_MAX_FBCS];
 	struct intel_frontbuffer_tracking fb_tracking;
 	struct intel_hotplug hotplug;
 	struct intel_opregion *opregion;
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index d9cab25d414a..dcdfcff80de3 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -69,7 +69,7 @@
 
 #define for_each_intel_fbc(__display, __fbc, __fbc_id) \
 	for_each_fbc_id((__display), (__fbc_id)) \
-		for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
+		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
 
 struct intel_fbc_funcs {
 	void (*activate)(struct intel_fbc *fbc);
@@ -2211,7 +2211,7 @@ void intel_fbc_init(struct intel_display *display)
 		    display->params.enable_fbc);
 
 	for_each_fbc_id(display, fbc_id)
-		display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
+		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
 }
 
 /**
@@ -2330,7 +2330,7 @@ void intel_fbc_debugfs_register(struct intel_display *display)
 {
 	struct intel_fbc *fbc;
 
-	fbc = display->fbc[INTEL_FBC_A];
+	fbc = display->fbc.instances[INTEL_FBC_A];
 	if (fbc)
 		intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
 }
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 89c8003ccfe7..48af74963e74 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2444,7 +2444,7 @@ static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
 	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
 
 	if (skl_plane_has_fbc(display, fbc_id, plane_id))
-		return display->fbc[fbc_id];
+		return display->fbc.instances[fbc_id];
 	else
 		return NULL;
 }
-- 
2.43.0

[PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Vinod Govindapillai]

One of the FBC instances can utilize the reserved area of SoC
level cache for the fbc transactions to benefit reduced memory
system power especially in idle scenarios. Reserved area of the
system cache can be assigned to an fbc instance by configuring
the cacheability configuration register with offset of the
compressed frame buffer in stolen memoty of that fbc. There is
a limit to this reserved area which is programmable and for
xe3p_lpd the limit is defined as 2MB.

v2: - better to track fbc sys cache usage from intel_display level,
      sanitize the cacheability config register on probe (Matt)
    - limit this for integrated graphics solutions, confirmed that
      no default value set for cache range by hw (Gustavo)

v3: - changes related to the use of fbc substruct in intel_display
    - use intel_de_write() instead of intel_rmw() by hardcoding the
      default value fields

Bspec: 68881, 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  3 +
 .../drm/i915/display/intel_display_device.h   |  1 +
 drivers/gpu/drm/i915/display/intel_fbc.c      | 93 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
 4 files changed, 107 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 58325f530670..f557c9293d33 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -400,6 +400,9 @@ struct intel_display {
 
 	struct {
 		struct intel_fbc *instances[I915_MAX_FBCS];
+
+		/* xe3p_lpd+ : FBC instance utlizing the system cache */
+		enum intel_fbc_id sys_cache_id;
 	} fbc;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index b559ef43d547..b74cb69ccc85 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -173,6 +173,7 @@ struct intel_display_platforms {
 #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
 #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
 #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
+#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
 #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
 #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
 #define HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index dcdfcff80de3..d7e913792518 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -71,6 +71,10 @@
 	for_each_fbc_id((__display), (__fbc_id)) \
 		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
 
+#define SYS_CACHE_FBC_INSTANCE_NONE			I915_MAX_FBCS
+#define IS_SYS_CACHE_FBC_INSTANCE_NONE(__display)	((__display)->fbc.sys_cache_id == SYS_CACHE_FBC_INSTANCE_NONE)
+#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display, id)	((__display)->fbc.sys_cache_id == (id))
+
 struct intel_fbc_funcs {
 	void (*activate)(struct intel_fbc *fbc);
 	void (*deactivate)(struct intel_fbc *fbc);
@@ -941,6 +945,79 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 		fbc_compressor_clkgate_disable_wa(fbc, true);
 }
 
+static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display *display,
+					      enum intel_fbc_id fbc_id)
+{
+	display->fbc.sys_cache_id = fbc_id;
+}
+
+static void xe3p_lpd_fbc_commit_sys_cache_usage(struct intel_display *display,
+						u32 reg)
+{
+	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
+}
+
+static int xe3p_lpd_fbc_get_cache_limit(void)
+{
+	/* Default 2MB for xe3p_lpd */
+	return 2 * 1024 * 1024;
+}
+
+static void xe3p_lpd_fbc_clear_sys_cache_usage(struct intel_display *display)
+{
+	/* Clear all the fields except the default fields */
+	u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
+
+	xe3p_lpd_fbc_commit_sys_cache_usage(display, default_fields);
+
+	/* Mark that no FBC instance utilize the system cache */
+	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
+}
+
+static void xe3p_lpd_fbc_set_sys_cache_usage(const struct intel_fbc *fbc)
+{
+	struct intel_display *display = fbc->display;
+	/* limit to be configured to the register in 64k byte chunks */
+	int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
+	/* offset to be configured to the register in 4K byte chunks */
+	int offset = i915_gem_stolen_node_offset(fbc->compressed_fb) / (4 * 1024);
+	/* Cache read enable is enabled by default */
+	u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
+		    FBC_SYS_CACHEABLE_RANGE(range) |
+		    FBC_SYS_CACHE_START_BASE(offset) |
+		    FBC_SYS_CACHE_READ_ENABLE;
+
+	lockdep_assert_held(&fbc->lock);
+
+	xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
+
+	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
+}
+
+static void xe3p_lpd_fbc_update_sys_cache_usage(const struct intel_fbc *fbc,
+						bool set)
+{
+	struct intel_display *display = fbc->display;
+
+	lockdep_assert_held(&fbc->lock);
+
+	/* system cache for fbc already reserved */
+	if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
+		return;
+
+	/* cannot clear if "fbc" did not reserve the cache */
+	if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display, fbc->id))
+		return;
+
+	if (set)
+		xe3p_lpd_fbc_set_sys_cache_usage(fbc);
+	else
+		xe3p_lpd_fbc_clear_sys_cache_usage(display);
+
+	drm_dbg_kms(display->drm, "System cacheability usage for FBC[%d] %s\n",
+		    fbc->id, set ? "configured" : "cleared");
+}
+
 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 {
 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
@@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display *display)
 
 		kfree(fbc);
 	}
+
+	if (HAS_FBC_SYS_CACHE(display))
+		xe3p_lpd_fbc_clear_sys_cache_usage(display);
 }
 
 static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
@@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
 
 	__intel_fbc_cleanup_cfb(fbc);
 
+	if (HAS_FBC_SYS_CACHE(display))
+		xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
+
 	/* wa_18038517565 Enable DPFC clock gating after FBC disable */
 	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
 		fbc_compressor_clkgate_disable_wa(fbc, false);
@@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
 
 	intel_fbc_program_workarounds(fbc);
 	intel_fbc_program_cfb(fbc);
+
+	if (HAS_FBC_SYS_CACHE(display))
+		xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
 }
 
 /**
@@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display *display)
 
 	for_each_fbc_id(display, fbc_id)
 		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
+
+	/* Mark that no FBC instance is using the system cache */
+	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
 }
 
 /**
@@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display *display)
 		if (intel_fbc_hw_is_active(fbc))
 			intel_fbc_hw_deactivate(fbc);
 	}
+
+	/* Ensure the sys cache usage register gets cleared */
+	if (HAS_FBC_SYS_CACHE(display))
+		xe3p_lpd_fbc_clear_sys_cache_usage(display);
 }
 
 static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..d2d889fa4bed 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -126,4 +126,14 @@
 #define   FBC_REND_NUKE			REG_BIT(2)
 #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
 
+#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
+#define   FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
+#define   FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
+#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
+#define   FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
+#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
+#define   FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
+#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
+#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
+
 #endif /* __INTEL_FBC_REGS__ */
-- 
2.43.0

Re: [PATCH v3 1/2] drm/i915/display: Use a sub-struct for fbc operations in intel_display

[Jani Nikula]

On Sun, 23 Nov 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> As FBC can utilze the system cache in xe3p_lpd onwards, we need

*utilize

> a way to track which fbc instance is utilizing this cache. So we
> would need to extend the intel_display with such a functionality.
> Introduce a new fbc substruct and move the current fbc instance
> array into that. Then the following patch can utilize this to
> introduce functionaity to configure and track the system cache
> usage by the fbc instance.

In general, please don't refer to "patches" in commit messages. Just
consider reading this commit message a year from now, wondering what
"the following patch" might refer to.

No need to resend for this.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> Suggested-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_plane.c          | 2 +-
>  drivers/gpu/drm/i915/display/intel_display_core.h  | 5 ++++-
>  drivers/gpu/drm/i915/display/intel_fbc.c           | 6 +++---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
>  4 files changed, 9 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index 51ccc6bd5f21..2c40bc632b3d 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -134,7 +134,7 @@ static struct intel_fbc *i9xx_plane_fbc(struct intel_display *display,
>  					enum i9xx_plane_id i9xx_plane)
>  {
>  	if (i9xx_plane_has_fbc(display, i9xx_plane))
> -		return display->fbc[INTEL_FBC_A];
> +		return display->fbc.instances[INTEL_FBC_A];
>  	else
>  		return NULL;
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 9b36654b593d..58325f530670 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -398,6 +398,10 @@ struct intel_display {
>  		const struct dram_info *info;
>  	} dram;
>  
> +	struct {
> +		struct intel_fbc *instances[I915_MAX_FBCS];
> +	} fbc;
> +
>  	struct {
>  		/* list of fbdev register on this device */
>  		struct intel_fbdev *fbdev;
> @@ -615,7 +619,6 @@ struct intel_display {
>  	struct drm_dp_tunnel_mgr *dp_tunnel_mgr;
>  	struct intel_audio audio;
>  	struct intel_dpll_global dpll;
> -	struct intel_fbc *fbc[I915_MAX_FBCS];
>  	struct intel_frontbuffer_tracking fb_tracking;
>  	struct intel_hotplug hotplug;
>  	struct intel_opregion *opregion;
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index d9cab25d414a..dcdfcff80de3 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -69,7 +69,7 @@
>  
>  #define for_each_intel_fbc(__display, __fbc, __fbc_id) \
>  	for_each_fbc_id((__display), (__fbc_id)) \
> -		for_each_if((__fbc) = (__display)->fbc[(__fbc_id)])
> +		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
>  
>  struct intel_fbc_funcs {
>  	void (*activate)(struct intel_fbc *fbc);
> @@ -2211,7 +2211,7 @@ void intel_fbc_init(struct intel_display *display)
>  		    display->params.enable_fbc);
>  
>  	for_each_fbc_id(display, fbc_id)
> -		display->fbc[fbc_id] = intel_fbc_create(display, fbc_id);
> +		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
>  }
>  
>  /**
> @@ -2330,7 +2330,7 @@ void intel_fbc_debugfs_register(struct intel_display *display)
>  {
>  	struct intel_fbc *fbc;
>  
> -	fbc = display->fbc[INTEL_FBC_A];
> +	fbc = display->fbc.instances[INTEL_FBC_A];
>  	if (fbc)
>  		intel_fbc_debugfs_add(fbc, display->drm->debugfs_root);
>  }
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 89c8003ccfe7..48af74963e74 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2444,7 +2444,7 @@ static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
>  	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
>  
>  	if (skl_plane_has_fbc(display, fbc_id, plane_id))
> -		return display->fbc[fbc_id];
> +		return display->fbc.instances[fbc_id];
>  	else
>  		return NULL;
>  }

-- 
Jani Nikula, Intel

Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Jani Nikula]

On Sun, 23 Nov 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> One of the FBC instances can utilize the reserved area of SoC
> level cache for the fbc transactions to benefit reduced memory
> system power especially in idle scenarios. Reserved area of the
> system cache can be assigned to an fbc instance by configuring
> the cacheability configuration register with offset of the
> compressed frame buffer in stolen memoty of that fbc. There is
> a limit to this reserved area which is programmable and for
> xe3p_lpd the limit is defined as 2MB.
>
> v2: - better to track fbc sys cache usage from intel_display level,
>       sanitize the cacheability config register on probe (Matt)
>     - limit this for integrated graphics solutions, confirmed that
>       no default value set for cache range by hw (Gustavo)
>
> v3: - changes related to the use of fbc substruct in intel_display
>     - use intel_de_write() instead of intel_rmw() by hardcoding the
>       default value fields
>

I think overall the implementation feels a bit overwhelming. I mean
there are so many functions, so many checks, to the point of being
excessive.

Some comments inline.

> Bspec: 68881, 74722
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  3 +
>  .../drm/i915/display/intel_display_device.h   |  1 +
>  drivers/gpu/drm/i915/display/intel_fbc.c      | 93 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
>  4 files changed, 107 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 58325f530670..f557c9293d33 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -400,6 +400,9 @@ struct intel_display {
>  
>  	struct {
>  		struct intel_fbc *instances[I915_MAX_FBCS];
> +
> +		/* xe3p_lpd+ : FBC instance utlizing the system cache */

Please no space before :, *utilizing

> +		enum intel_fbc_id sys_cache_id;
>  	} fbc;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index b559ef43d547..b74cb69ccc85 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -173,6 +173,7 @@ struct intel_display_platforms {
>  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >= 12 && HAS_DSC(__display))
>  #define HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >= 30)
> +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >= 35 && !(__display)->platform.dgfx)
>  #define HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
>  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >= 3)
>  #define HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index dcdfcff80de3..d7e913792518 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -71,6 +71,10 @@
>  	for_each_fbc_id((__display), (__fbc_id)) \
>  		for_each_if((__fbc) = (__display)->fbc.instances[(__fbc_id)])
>  
> +#define SYS_CACHE_FBC_INSTANCE_NONE			I915_MAX_FBCS
> +#define IS_SYS_CACHE_FBC_INSTANCE_NONE(__display)	((__display)->fbc.sys_cache_id == SYS_CACHE_FBC_INSTANCE_NONE)

The only user of this has !IS_SYS_CACHE_FBC_INSTANCE_NONE(display)
i.e. "if not none".

Would be more useful to check if it's "set" or "valid", and avoid the
double negative. And use a shorter name. Maybe a static inline function.

But I'm not even sure the display->fbc.sys_cache_id needs to be
abstracted away. It's not a complicated thing, and, more importantly,
it's all within the same file. If outside access was needed, yes,
abstract, but here, not convinced.

Maybe:

	if (fbc_sys_cache_id_valid(display->fbc.sys_cache_id))

I also don't think *all* of these functions should be prefixed with
xe3p_lpd_ because that's a monster, and makes all of this difficult to
read.

> +#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display, id)	((__display)->fbc.sys_cache_id == (id))

I think this feels cumbersome. Why not just check

	if (display->fbc.sys_cache_id == id)

inline, and it's obvious?

> +
>  struct intel_fbc_funcs {
>  	void (*activate)(struct intel_fbc *fbc);
>  	void (*deactivate)(struct intel_fbc *fbc);
> @@ -941,6 +945,79 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
>  		fbc_compressor_clkgate_disable_wa(fbc, true);
>  }
>  
> +static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display *display,
> +					      enum intel_fbc_id fbc_id)
> +{
> +	display->fbc.sys_cache_id = fbc_id;
> +}

Again, I'm not sure if this function is really needed. Just inline?

> +
> +static void xe3p_lpd_fbc_commit_sys_cache_usage(struct intel_display *display,
> +						u32 reg)
> +{
> +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG, reg);
> +}

Not sure if this is needed. Just inline?

> +
> +static int xe3p_lpd_fbc_get_cache_limit(void)
> +{
> +	/* Default 2MB for xe3p_lpd */
> +	return 2 * 1024 * 1024;
> +}

Ditto. Especially odd how this multiplies and the user the divides by 64
* 1024.

> +
> +static void xe3p_lpd_fbc_clear_sys_cache_usage(struct intel_display *display)
> +{
> +	/* Clear all the fields except the default fields */
> +	u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
> +
> +	xe3p_lpd_fbc_commit_sys_cache_usage(display, default_fields);
> +
> +	/* Mark that no FBC instance utilize the system cache */
> +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
> +}

My point above is that this function only calls wrappers and really does
nothing itself. It's too many layers for a simple thing.

fbc_sys_cache_disable()?

> +
> +static void xe3p_lpd_fbc_set_sys_cache_usage(const struct intel_fbc *fbc)
> +{
> +	struct intel_display *display = fbc->display;
> +	/* limit to be configured to the register in 64k byte chunks */
> +	int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
> +	/* offset to be configured to the register in 4K byte chunks */
> +	int offset = i915_gem_stolen_node_offset(fbc->compressed_fb) / (4 * 1024);
> +	/* Cache read enable is enabled by default */
> +	u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> +		    FBC_SYS_CACHEABLE_RANGE(range) |
> +		    FBC_SYS_CACHE_START_BASE(offset) |
> +		    FBC_SYS_CACHE_READ_ENABLE;
> +
> +	lockdep_assert_held(&fbc->lock);
> +
> +	xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
> +
> +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
> +}

Ditto.

fbc_sys_cache_enable()?

> +
> +static void xe3p_lpd_fbc_update_sys_cache_usage(const struct intel_fbc *fbc,
> +						bool set)
> +{
> +	struct intel_display *display = fbc->display;
> +
> +	lockdep_assert_held(&fbc->lock);
> +
> +	/* system cache for fbc already reserved */
> +	if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
> +		return;
> +
> +	/* cannot clear if "fbc" did not reserve the cache */
> +	if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display, fbc->id))
> +		return;
> +
> +	if (set)
> +		xe3p_lpd_fbc_set_sys_cache_usage(fbc);
> +	else
> +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
> +
> +	drm_dbg_kms(display->drm, "System cacheability usage for FBC[%d] %s\n",
> +		    fbc->id, set ? "configured" : "cleared");
> +}

Most of this function is two separate paths based on the parameter. I
think it would benefit from actually being two separate functions. So
why not just merge this with xe3p_lpd_fbc_set_sys_cache_usage() and
xe3p_lpd_fbc_clear_sys_cache_usage()?

> +
>  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>  {
>  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> @@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display *display)
>  
>  		kfree(fbc);
>  	}
> +
> +	if (HAS_FBC_SYS_CACHE(display))
> +		xe3p_lpd_fbc_clear_sys_cache_usage(display);

I don't think this should check for HAS_FBC_SYS_CACHE(). I think
internally the function being called should check if sys cache has been
set. And make sure it's only set on where it's available.

>  }
>  
>  static bool i8xx_fbc_stride_is_valid(const struct intel_plane_state *plane_state)
> @@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct intel_fbc *fbc)
>  
>  	__intel_fbc_cleanup_cfb(fbc);
>  
> +	if (HAS_FBC_SYS_CACHE(display))
> +		xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
> +

Ditto. I'm also not sure why some places call the version with params,
and some others the version without params.

>  	/* wa_18038517565 Enable DPFC clock gating after FBC disable */
>  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
>  		fbc_compressor_clkgate_disable_wa(fbc, false);
> @@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct intel_atomic_state *state,
>  
>  	intel_fbc_program_workarounds(fbc);
>  	intel_fbc_program_cfb(fbc);
> +
> +	if (HAS_FBC_SYS_CACHE(display))
> +		xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);

xe3p_lpd_fbc_update_sys_cache_usage() is the function that should check
for HAS_FBC_SYS_CACHE() in one place.

Well, maybe it should be renamed fbc_sys_cache_enable().

>  }
>  
>  /**
> @@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display *display)
>  
>  	for_each_fbc_id(display, fbc_id)
>  		display->fbc.instances[fbc_id] = intel_fbc_create(display, fbc_id);
> +
> +	/* Mark that no FBC instance is using the system cache */
> +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, SYS_CACHE_FBC_INSTANCE_NONE);
>  }
>  
>  /**
> @@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display *display)
>  		if (intel_fbc_hw_is_active(fbc))
>  			intel_fbc_hw_deactivate(fbc);
>  	}
> +
> +	/* Ensure the sys cache usage register gets cleared */
> +	if (HAS_FBC_SYS_CACHE(display))
> +		xe3p_lpd_fbc_clear_sys_cache_usage(display);

Ditto about checking for valid sys cache inside, not
HAS_FBC_SYS_CACHE().

>  }
>  
>  static int intel_fbc_debugfs_status_show(struct seq_file *m, void *unused)
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> index b1d0161a3196..d2d889fa4bed 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> @@ -126,4 +126,14 @@
>  #define   FBC_REND_NUKE			REG_BIT(2)
>  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
>  
> +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
> +#define   FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
> +#define   FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
> +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
> +#define   FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
> +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
> +#define   FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
> +#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
> +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
> +
>  #endif /* __INTEL_FBC_REGS__ */

-- 
Jani Nikula, Intel

Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Govindapillai, Vinod]

Hi Jani,

Thanks for the input.. replies inline...

On Mon, 2025-11-24 at 13:27 +0200, Jani Nikula wrote:
> On Sun, 23 Nov 2025, Vinod Govindapillai
> <vinod.govindapillai@intel.com> wrote:
> > One of the FBC instances can utilize the reserved area of SoC
> > level cache for the fbc transactions to benefit reduced memory
> > system power especially in idle scenarios. Reserved area of the
> > system cache can be assigned to an fbc instance by configuring
> > the cacheability configuration register with offset of the
> > compressed frame buffer in stolen memoty of that fbc. There is
> > a limit to this reserved area which is programmable and for
> > xe3p_lpd the limit is defined as 2MB.
> > 
> > v2: - better to track fbc sys cache usage from intel_display level,
> >       sanitize the cacheability config register on probe (Matt)
> >     - limit this for integrated graphics solutions, confirmed that
> >       no default value set for cache range by hw (Gustavo)
> > 
> > v3: - changes related to the use of fbc substruct in intel_display
> >     - use intel_de_write() instead of intel_rmw() by hardcoding the
> >       default value fields
> > 
> 
> I think overall the implementation feels a bit overwhelming. I mean
> there are so many functions, so many checks, to the point of being
> excessive.
> 
> Some comments inline.
> 
> > Bspec: 68881, 74722
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_core.h |  3 +
> >  .../drm/i915/display/intel_display_device.h   |  1 +
> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 93
> > +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
> >  4 files changed, 107 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 58325f530670..f557c9293d33 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -400,6 +400,9 @@ struct intel_display {
> >  
> >  	struct {
> >  		struct intel_fbc *instances[I915_MAX_FBCS];
> > +
> > +		/* xe3p_lpd+ : FBC instance utlizing the system
> > cache */
> 
> Please no space before :, *utilizing
> 
> > +		enum intel_fbc_id sys_cache_id;
> >  	} fbc;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
> > b/drivers/gpu/drm/i915/display/intel_display_device.h
> > index b559ef43d547..b74cb69ccc85 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> > @@ -173,6 +173,7 @@ struct intel_display_platforms {
> >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
> > 12 && HAS_DSC(__display))
> >  #define
> > HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
> >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
> > 30)
> > +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
> > 35 && !(__display)->platform.dgfx)
> >  #define
> > HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
> >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
> > 3)
> >  #define
> > HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
> > b/drivers/gpu/drm/i915/display/intel_fbc.c
> > index dcdfcff80de3..d7e913792518 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> > @@ -71,6 +71,10 @@
> >  	for_each_fbc_id((__display), (__fbc_id)) \
> >  		for_each_if((__fbc) = (__display)-
> > >fbc.instances[(__fbc_id)])
> >  
> > +#define
> > SYS_CACHE_FBC_INSTANCE_NONE			I915_MAX_FBCS
> > +#define
> > IS_SYS_CACHE_FBC_INSTANCE_NONE(__display)	((__display)->fbc.sys_cache_id==SYS_CACHE_FBC_INSTANCE_NONE)
> 
> The only user of this has !IS_SYS_CACHE_FBC_INSTANCE_NONE(display)
> i.e. "if not none".
> 
> Would be more useful to check if it's "set" or "valid", and avoid the
> double negative. And use a shorter name. Maybe a static inline
> function.
> 
> But I'm not even sure the display->fbc.sys_cache_id needs to be
> abstracted away. It's not a complicated thing, and, more importantly,
> it's all within the same file. If outside access was needed, yes,
> abstract, but here, not convinced.
> 
> Maybe:
> 
> 	if (fbc_sys_cache_id_valid(display->fbc.sys_cache_id))
> 
> I also don't think *all* of these functions should be prefixed with
> xe3p_lpd_ because that's a monster, and makes all of this difficult
> to
> read.
> 
> > +#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display,
> > id)	((__display)->fbc.sys_cache_id == (id))
> 
> I think this feels cumbersome. Why not just check
> 
> 	if (display->fbc.sys_cache_id == id)
> 
> inline, and it's obvious?
> 
> > +
> >  struct intel_fbc_funcs {
> >  	void (*activate)(struct intel_fbc *fbc);
> >  	void (*deactivate)(struct intel_fbc *fbc);
> > @@ -941,6 +945,79 @@ static void
> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
> >  		fbc_compressor_clkgate_disable_wa(fbc, true);
> >  }
> >  
> > +static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display
> > *display,
> > +					      enum intel_fbc_id
> > fbc_id)
> > +{
> > +	display->fbc.sys_cache_id = fbc_id;
> > +}
> 
> Again, I'm not sure if this function is really needed. Just inline?

Ack for the above suggestions. About the function naming, yeah it is
indeed bit complex, but was following the functions names being
followed in this file. Should it be prefixed with nvl /intel or just
fbc?  instead? Any suggestion?

> 
> > +
> > +static void xe3p_lpd_fbc_commit_sys_cache_usage(struct
> > intel_display *display,
> > +						u32 reg)
> > +{
> > +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
> > reg);
> > +}
> 
> Not sure if this is needed. Just inline?

Two paths update this register - setting up the cache for a fbc and
clearing it. Also soon there is going to be a workaround implemented
which we need to disable the read cache enable bit which is set on by
default. So I was thinking of intercept here and apply the wa

if (intel_display_wa(display, xxxx))
		reg &= ~FBC_SYS_CACHE_READ_ENABLE;

> 
> > +
> > +static int xe3p_lpd_fbc_get_cache_limit(void)
> > +{
> > +	/* Default 2MB for xe3p_lpd */
> > +	return 2 * 1024 * 1024;
> > +}
> 
> Ditto. Especially odd how this multiplies and the user the divides by
> 64
> * 1024.

Initially from HAS my understanding was that this was supposed to be
set by a pre-os fw and driver dont modify this field. And this can
change per platform. But from the recent logs fro, these fields are set
as 0 and has to be programmed by the driver. (I am clarifying this with
the HW team). Anyway, this need to be variated per platform. In some
other component such 2MB was hard coded like this. So thought of
adopting that. Any suggestion?


> > +
> > +static void xe3p_lpd_fbc_clear_sys_cache_usage(struct
> > intel_display *display)
> > +{
> > +	/* Clear all the fields except the default fields */
> > +	u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
> > +
> > +	xe3p_lpd_fbc_commit_sys_cache_usage(display,
> > default_fields);
> > +
> > +	/* Mark that no FBC instance utilize the system cache */
> > +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
> > SYS_CACHE_FBC_INSTANCE_NONE);
> > +}
> 
> My point above is that this function only calls wrappers and really
> does
> nothing itself. It's too many layers for a simple thing.
> 
> fbc_sys_cache_disable()?
> 
> > +
> > +static void xe3p_lpd_fbc_set_sys_cache_usage(const struct
> > intel_fbc *fbc)
> > +{
> > +	struct intel_display *display = fbc->display;
> > +	/* limit to be configured to the register in 64k byte
> > chunks */
> > +	int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
> > +	/* offset to be configured to the register in 4K byte
> > chunks */
> > +	int offset = i915_gem_stolen_node_offset(fbc-
> > >compressed_fb) / (4 * 1024);
> > +	/* Cache read enable is enabled by default */
> > +	u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
> > +		    FBC_SYS_CACHEABLE_RANGE(range) |
> > +		    FBC_SYS_CACHE_START_BASE(offset) |
> > +		    FBC_SYS_CACHE_READ_ENABLE;
> > +
> > +	lockdep_assert_held(&fbc->lock);
> > +
> > +	xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
> > +
> > +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
> > +}
> 
> Ditto.
> 
> fbc_sys_cache_enable()?
> 
> > +
> > +static void xe3p_lpd_fbc_update_sys_cache_usage(const struct
> > intel_fbc *fbc,
> > +						bool set)
> > +{
> > +	struct intel_display *display = fbc->display;
> > +
> > +	lockdep_assert_held(&fbc->lock);
> > +
> > +	/* system cache for fbc already reserved */
> > +	if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
> > +		return;
> > +
> > +	/* cannot clear if "fbc" did not reserve the cache */
> > +	if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display,
> > fbc->id))
> > +		return;
> > +
> > +	if (set)
> > +		xe3p_lpd_fbc_set_sys_cache_usage(fbc);
> > +	else
> > +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
> > +
> > +	drm_dbg_kms(display->drm, "System cacheability usage for
> > FBC[%d] %s\n",
> > +		    fbc->id, set ? "configured" : "cleared");
> > +}
> 
> Most of this function is two separate paths based on the parameter. I
> think it would benefit from actually being two separate functions. So
> why not just merge this with xe3p_lpd_fbc_set_sys_cache_usage() and
> xe3p_lpd_fbc_clear_sys_cache_usage()?

Actually there are three paths to update this register (two separate
path to clear this register)

1. As part of enable FBC - depends on the fbc instance (with fbc mutex
taken). If sys_cache is not reserved by any other instance.

2. As part of disable FBC - depends on the fbc instance to avoid
clearing if this fbc didnt reserve the cache space. (with fbc mutex
taken)

3. Clear this register as part of sanitize call (upon setup_hw_state()
calls upon probe and resume) and intel_fbc_cleanup() upon module
removal. Not depend on the fbc instance.

So something like this make sense?

fbc_program_sys_cache(u32 reg)
{
	intel_de_write(reg)
}

fbc_sys_cache_reset(display)
{
	if (!HAS_FBC_SYS_CACHE())
		return

	fbc_program_sys_cache(0)
	fbc.sys_cache_id = SYS_CACHE_FBC_INSTANCE_NONE
}

fbc_sys_cache_disable(fbc)
{
	if (!HAS_FBC_SYS_CACHE())
		return

	if (fbc.sys_cache_id != fbc->id)
		return;

	fbc_sys_cache_reset(display)
}

fbc_sys_cache_enable(fbc)
{
	if (!HAS_FBC_SYS_CACHE())
		return

	if (fbc.sys_cache_id != SYS_CACHE_FBC_INSTANCE_NONE)
		return;

	fbc_program_sys_cache(val)

	fbc.sys_cache_id = fbc-->id
}

intel_fbc_enable() will call fbc_sys_cache_enable(fbc)

__intel_fbc_disable() will call fbc_sys_cache_disable(fbc)

and 

intel_fbc_cleanup() and intel_fbc_sanitize() will call
fbc_sys_cache_reset(display) as a general cleanup for this register.



> 
> > +
> >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
> >  {
> >  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
> > @@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display
> > *display)
> >  
> >  		kfree(fbc);
> >  	}
> > +
> > +	if (HAS_FBC_SYS_CACHE(display))
> > +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
> 
> I don't think this should check for HAS_FBC_SYS_CACHE(). I think
> internally the function being called should check if sys cache has
> been
> set. And make sure it's only set on where it's available.
> 
> >  }
> >  
> >  static bool i8xx_fbc_stride_is_valid(const struct
> > intel_plane_state *plane_state)
> > @@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct
> > intel_fbc *fbc)
> >  
> >  	__intel_fbc_cleanup_cfb(fbc);
> >  
> > +	if (HAS_FBC_SYS_CACHE(display))
> > +		xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
> > +
> 
> Ditto. I'm also not sure why some places call the version with
> params,
> and some others the version without params.
> 
> >  	/* wa_18038517565 Enable DPFC clock gating after FBC
> > disable */
> >  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
> >  		fbc_compressor_clkgate_disable_wa(fbc, false);
> > @@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct
> > intel_atomic_state *state,
> >  
> >  	intel_fbc_program_workarounds(fbc);
> >  	intel_fbc_program_cfb(fbc);
> > +
> > +	if (HAS_FBC_SYS_CACHE(display))
> > +		xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
> 
> xe3p_lpd_fbc_update_sys_cache_usage() is the function that should
> check
> for HAS_FBC_SYS_CACHE() in one place.
> 
> Well, maybe it should be renamed fbc_sys_cache_enable().
> 
> >  }
> >  
> >  /**
> > @@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display
> > *display)
> >  
> >  	for_each_fbc_id(display, fbc_id)
> >  		display->fbc.instances[fbc_id] =
> > intel_fbc_create(display, fbc_id);
> > +
> > +	/* Mark that no FBC instance is using the system cache */
> > +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
> > SYS_CACHE_FBC_INSTANCE_NONE);
> >  }
> >  
> >  /**
> > @@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display
> > *display)
> >  		if (intel_fbc_hw_is_active(fbc))
> >  			intel_fbc_hw_deactivate(fbc);
> >  	}
> > +
> > +	/* Ensure the sys cache usage register gets cleared */
> > +	if (HAS_FBC_SYS_CACHE(display))
> > +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
> 
> Ditto about checking for valid sys cache inside, not
> HAS_FBC_SYS_CACHE().
> 
> >  }
> >  
> >  static int intel_fbc_debugfs_status_show(struct seq_file *m, void
> > *unused)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > index b1d0161a3196..d2d889fa4bed 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
> > @@ -126,4 +126,14 @@
> >  #define   FBC_REND_NUKE			REG_BIT(2)
> >  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
> >  
> > +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
> > +#define  
> > FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
> > +#define  
> > FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
> > +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
> > +#define  
> > FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
> > +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
> > +#define  
> > FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,0)
> > +#define  
> > FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
> > +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
> > +
> >  #endif /* __INTEL_FBC_REGS__ */
> 

Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Jani Nikula]

On Mon, 24 Nov 2025, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> Hi Jani,
>
> Thanks for the input.. replies inline...
>
> On Mon, 2025-11-24 at 13:27 +0200, Jani Nikula wrote:
>> On Sun, 23 Nov 2025, Vinod Govindapillai
>> <vinod.govindapillai@intel.com> wrote:
>> > One of the FBC instances can utilize the reserved area of SoC
>> > level cache for the fbc transactions to benefit reduced memory
>> > system power especially in idle scenarios. Reserved area of the
>> > system cache can be assigned to an fbc instance by configuring
>> > the cacheability configuration register with offset of the
>> > compressed frame buffer in stolen memoty of that fbc. There is
>> > a limit to this reserved area which is programmable and for
>> > xe3p_lpd the limit is defined as 2MB.
>> > 
>> > v2: - better to track fbc sys cache usage from intel_display level,
>> >       sanitize the cacheability config register on probe (Matt)
>> >     - limit this for integrated graphics solutions, confirmed that
>> >       no default value set for cache range by hw (Gustavo)
>> > 
>> > v3: - changes related to the use of fbc substruct in intel_display
>> >     - use intel_de_write() instead of intel_rmw() by hardcoding the
>> >       default value fields
>> > 
>> 
>> I think overall the implementation feels a bit overwhelming. I mean
>> there are so many functions, so many checks, to the point of being
>> excessive.
>> 
>> Some comments inline.
>> 
>> > Bspec: 68881, 74722
>> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
>> > ---
>> >  .../gpu/drm/i915/display/intel_display_core.h |  3 +
>> >  .../drm/i915/display/intel_display_device.h   |  1 +
>> >  drivers/gpu/drm/i915/display/intel_fbc.c      | 93
>> > +++++++++++++++++++
>> >  drivers/gpu/drm/i915/display/intel_fbc_regs.h | 10 ++
>> >  4 files changed, 107 insertions(+)
>> > 
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > index 58325f530670..f557c9293d33 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> > @@ -400,6 +400,9 @@ struct intel_display {
>> >  
>> >  	struct {
>> >  		struct intel_fbc *instances[I915_MAX_FBCS];
>> > +
>> > +		/* xe3p_lpd+ : FBC instance utlizing the system
>> > cache */
>> 
>> Please no space before :, *utilizing
>> 
>> > +		enum intel_fbc_id sys_cache_id;
>> >  	} fbc;
>> >  
>> >  	struct {
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h
>> > b/drivers/gpu/drm/i915/display/intel_display_device.h
>> > index b559ef43d547..b74cb69ccc85 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display_device.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
>> > @@ -173,6 +173,7 @@ struct intel_display_platforms {
>> >  #define HAS_DSC_MST(__display)		(DISPLAY_VER(__display) >=
>> > 12 && HAS_DSC(__display))
>> >  #define
>> > HAS_FBC(__display)		(DISPLAY_RUNTIME_INFO(__display)->fbc_mask != 0)
>> >  #define HAS_FBC_DIRTY_RECT(__display)	(DISPLAY_VER(__display) >=
>> > 30)
>> > +#define HAS_FBC_SYS_CACHE(__display)	(DISPLAY_VER(__display) >=
>> > 35 && !(__display)->platform.dgfx)
>> >  #define
>> > HAS_FPGA_DBG_UNCLAIMED(__display)	(DISPLAY_INFO(__display)->has_fpga_dbg)
>> >  #define HAS_FW_BLC(__display)		(DISPLAY_VER(__display) >=
>> > 3)
>> >  #define
>> > HAS_GMBUS_BURST_READ(__display)	(DISPLAY_VER(__display) >= 10 || (__display)->platform.kabylake)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > index dcdfcff80de3..d7e913792518 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
>> > @@ -71,6 +71,10 @@
>> >  	for_each_fbc_id((__display), (__fbc_id)) \
>> >  		for_each_if((__fbc) = (__display)-
>> > >fbc.instances[(__fbc_id)])
>> >  
>> > +#define
>> > SYS_CACHE_FBC_INSTANCE_NONE			I915_MAX_FBCS
>> > +#define
>> > IS_SYS_CACHE_FBC_INSTANCE_NONE(__display)	((__display)->fbc.sys_cache_id==SYS_CACHE_FBC_INSTANCE_NONE)
>> 
>> The only user of this has !IS_SYS_CACHE_FBC_INSTANCE_NONE(display)
>> i.e. "if not none".
>> 
>> Would be more useful to check if it's "set" or "valid", and avoid the
>> double negative. And use a shorter name. Maybe a static inline
>> function.
>> 
>> But I'm not even sure the display->fbc.sys_cache_id needs to be
>> abstracted away. It's not a complicated thing, and, more importantly,
>> it's all within the same file. If outside access was needed, yes,
>> abstract, but here, not convinced.
>> 
>> Maybe:
>> 
>> 	if (fbc_sys_cache_id_valid(display->fbc.sys_cache_id))
>> 
>> I also don't think *all* of these functions should be prefixed with
>> xe3p_lpd_ because that's a monster, and makes all of this difficult
>> to
>> read.
>> 
>> > +#define IS_SYS_CACHE_FBC_INSTANCE_EQUALS(__display,
>> > id)	((__display)->fbc.sys_cache_id == (id))
>> 
>> I think this feels cumbersome. Why not just check
>> 
>> 	if (display->fbc.sys_cache_id == id)
>> 
>> inline, and it's obvious?
>> 
>> > +
>> >  struct intel_fbc_funcs {
>> >  	void (*activate)(struct intel_fbc *fbc);
>> >  	void (*deactivate)(struct intel_fbc *fbc);
>> > @@ -941,6 +945,79 @@ static void
>> > intel_fbc_program_workarounds(struct intel_fbc *fbc)
>> >  		fbc_compressor_clkgate_disable_wa(fbc, true);
>> >  }
>> >  
>> > +static void xe3p_lpd_fbc_set_sys_cache_fbc_id(struct intel_display
>> > *display,
>> > +					      enum intel_fbc_id
>> > fbc_id)
>> > +{
>> > +	display->fbc.sys_cache_id = fbc_id;
>> > +}
>> 
>> Again, I'm not sure if this function is really needed. Just inline?
>
> Ack for the above suggestions. About the function naming, yeah it is
> indeed bit complex, but was following the functions names being
> followed in this file. Should it be prefixed with nvl /intel or just
> fbc?  instead? Any suggestion?

I would honestly just go with fbc_sys_cache_ for all of them. We don't
have to prefix everything in the world with a platform that started a
new feature.

It's different when you deviate from existing functionality for a
platform, and need different implementations for different platforms.

>
>> 
>> > +
>> > +static void xe3p_lpd_fbc_commit_sys_cache_usage(struct
>> > intel_display *display,
>> > +						u32 reg)
>> > +{
>> > +	intel_de_write(display, XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG,
>> > reg);
>> > +}
>> 
>> Not sure if this is needed. Just inline?
>
> Two paths update this register - setting up the cache for a fbc and
> clearing it. Also soon there is going to be a workaround implemented
> which we need to disable the read cache enable bit which is set on by
> default. So I was thinking of intercept here and apply the wa
>
> if (intel_display_wa(display, xxxx))
> 		reg &= ~FBC_SYS_CACHE_READ_ENABLE;
>
>> 
>> > +
>> > +static int xe3p_lpd_fbc_get_cache_limit(void)
>> > +{
>> > +	/* Default 2MB for xe3p_lpd */
>> > +	return 2 * 1024 * 1024;
>> > +}
>> 
>> Ditto. Especially odd how this multiplies and the user the divides by
>> 64
>> * 1024.
>
> Initially from HAS my understanding was that this was supposed to be
> set by a pre-os fw and driver dont modify this field. And this can
> change per platform. But from the recent logs fro, these fields are set
> as 0 and has to be programmed by the driver. (I am clarifying this with
> the HW team). Anyway, this need to be variated per platform. In some
> other component such 2MB was hard coded like this. So thought of
> adopting that. Any suggestion?

Okay. But if the function needs to do platform deviation, you'll need to
pass display to it.

>
>
>> > +
>> > +static void xe3p_lpd_fbc_clear_sys_cache_usage(struct
>> > intel_display *display)
>> > +{
>> > +	/* Clear all the fields except the default fields */
>> > +	u32 default_fields = FBC_SYS_CACHE_READ_ENABLE;
>> > +
>> > +	xe3p_lpd_fbc_commit_sys_cache_usage(display,
>> > default_fields);
>> > +
>> > +	/* Mark that no FBC instance utilize the system cache */
>> > +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
>> > SYS_CACHE_FBC_INSTANCE_NONE);
>> > +}
>> 
>> My point above is that this function only calls wrappers and really
>> does
>> nothing itself. It's too many layers for a simple thing.
>> 
>> fbc_sys_cache_disable()?
>> 
>> > +
>> > +static void xe3p_lpd_fbc_set_sys_cache_usage(const struct
>> > intel_fbc *fbc)
>> > +{
>> > +	struct intel_display *display = fbc->display;
>> > +	/* limit to be configured to the register in 64k byte
>> > chunks */
>> > +	int range = xe3p_lpd_fbc_get_cache_limit() / (64 * 1024);
>> > +	/* offset to be configured to the register in 4K byte
>> > chunks */
>> > +	int offset = i915_gem_stolen_node_offset(fbc-
>> > >compressed_fb) / (4 * 1024);
>> > +	/* Cache read enable is enabled by default */
>> > +	u32 usage = FBC_SYS_CACHE_TAG_USE_RES_SPACE |
>> > +		    FBC_SYS_CACHEABLE_RANGE(range) |
>> > +		    FBC_SYS_CACHE_START_BASE(offset) |
>> > +		    FBC_SYS_CACHE_READ_ENABLE;
>> > +
>> > +	lockdep_assert_held(&fbc->lock);
>> > +
>> > +	xe3p_lpd_fbc_commit_sys_cache_usage(display, usage);
>> > +
>> > +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display, fbc->id);
>> > +}
>> 
>> Ditto.
>> 
>> fbc_sys_cache_enable()?
>> 
>> > +
>> > +static void xe3p_lpd_fbc_update_sys_cache_usage(const struct
>> > intel_fbc *fbc,
>> > +						bool set)
>> > +{
>> > +	struct intel_display *display = fbc->display;
>> > +
>> > +	lockdep_assert_held(&fbc->lock);
>> > +
>> > +	/* system cache for fbc already reserved */
>> > +	if (set && !IS_SYS_CACHE_FBC_INSTANCE_NONE(display))
>> > +		return;
>> > +
>> > +	/* cannot clear if "fbc" did not reserve the cache */
>> > +	if (!set && !IS_SYS_CACHE_FBC_INSTANCE_EQUALS(display,
>> > fbc->id))
>> > +		return;
>> > +
>> > +	if (set)
>> > +		xe3p_lpd_fbc_set_sys_cache_usage(fbc);
>> > +	else
>> > +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
>> > +
>> > +	drm_dbg_kms(display->drm, "System cacheability usage for
>> > FBC[%d] %s\n",
>> > +		    fbc->id, set ? "configured" : "cleared");
>> > +}
>> 
>> Most of this function is two separate paths based on the parameter. I
>> think it would benefit from actually being two separate functions. So
>> why not just merge this with xe3p_lpd_fbc_set_sys_cache_usage() and
>> xe3p_lpd_fbc_clear_sys_cache_usage()?
>
> Actually there are three paths to update this register (two separate
> path to clear this register)
>
> 1. As part of enable FBC - depends on the fbc instance (with fbc mutex
> taken). If sys_cache is not reserved by any other instance.
>
> 2. As part of disable FBC - depends on the fbc instance to avoid
> clearing if this fbc didnt reserve the cache space. (with fbc mutex
> taken)
>
> 3. Clear this register as part of sanitize call (upon setup_hw_state()
> calls upon probe and resume) and intel_fbc_cleanup() upon module
> removal. Not depend on the fbc instance.

Shouldn't fbc have been disabled by the time of module removal? I think
the per fbc disable should've been called already, no?

I think you could add a drm_WARN_ON(fbc.sys_cache_id !=
SYS_CACHE_FBC_INSTANCE_NONE) in the module removal path instead.

Btw that could also be renamed FBC_SYS_CACHE_ID_NONE or something.

> So something like this make sense?
>
> fbc_program_sys_cache(u32 reg)
> {
> 	intel_de_write(reg)
> }

I'm personally not a fan of "program" in pretty much any function
naming. What does it mean to program something? Isn't the whole driver
programming the hardare?

Just fbc_sys_cache_write()?

> fbc_sys_cache_reset(display)
> {
> 	if (!HAS_FBC_SYS_CACHE())
> 		return
>
> 	fbc_program_sys_cache(0)
> 	fbc.sys_cache_id = SYS_CACHE_FBC_INSTANCE_NONE
> }
>
> fbc_sys_cache_disable(fbc)
> {
> 	if (!HAS_FBC_SYS_CACHE())
> 		return

You don't need this check, because...

>
> 	if (fbc.sys_cache_id != fbc->id)
> 		return;

...this will catch the same conditions.

>
> 	fbc_sys_cache_reset(display)
> }
>
> fbc_sys_cache_enable(fbc)
> {
> 	if (!HAS_FBC_SYS_CACHE())
> 		return
>
> 	if (fbc.sys_cache_id != SYS_CACHE_FBC_INSTANCE_NONE)
> 		return;
>
> 	fbc_program_sys_cache(val)
>
> 	fbc.sys_cache_id = fbc-->id
> }
>
> intel_fbc_enable() will call fbc_sys_cache_enable(fbc)
>
> __intel_fbc_disable() will call fbc_sys_cache_disable(fbc)
>
> and 
>
> intel_fbc_cleanup() and intel_fbc_sanitize() will call
> fbc_sys_cache_reset(display) as a general cleanup for this register.

Overall sounds better, but I'll probably need to see the patches to
grasp it.

The fbc debugfs should also have the info on whether the instance is
using the sys cache.


BR,
Jani.


>
>
>
>> 
>> > +
>> >  static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
>> >  {
>> >  	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
>> > @@ -967,6 +1044,9 @@ void intel_fbc_cleanup(struct intel_display
>> > *display)
>> >  
>> >  		kfree(fbc);
>> >  	}
>> > +
>> > +	if (HAS_FBC_SYS_CACHE(display))
>> > +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
>> 
>> I don't think this should check for HAS_FBC_SYS_CACHE(). I think
>> internally the function being called should check if sys cache has
>> been
>> set. And make sure it's only set on where it's available.
>> 
>> >  }
>> >  
>> >  static bool i8xx_fbc_stride_is_valid(const struct
>> > intel_plane_state *plane_state)
>> > @@ -1780,6 +1860,9 @@ static void __intel_fbc_disable(struct
>> > intel_fbc *fbc)
>> >  
>> >  	__intel_fbc_cleanup_cfb(fbc);
>> >  
>> > +	if (HAS_FBC_SYS_CACHE(display))
>> > +		xe3p_lpd_fbc_update_sys_cache_usage(fbc, false);
>> > +
>> 
>> Ditto. I'm also not sure why some places call the version with
>> params,
>> and some others the version without params.
>> 
>> >  	/* wa_18038517565 Enable DPFC clock gating after FBC
>> > disable */
>> >  	if (display->platform.dg2 || DISPLAY_VER(display) >= 14)
>> >  		fbc_compressor_clkgate_disable_wa(fbc, false);
>> > @@ -1972,6 +2055,9 @@ static void __intel_fbc_enable(struct
>> > intel_atomic_state *state,
>> >  
>> >  	intel_fbc_program_workarounds(fbc);
>> >  	intel_fbc_program_cfb(fbc);
>> > +
>> > +	if (HAS_FBC_SYS_CACHE(display))
>> > +		xe3p_lpd_fbc_update_sys_cache_usage(fbc, true);
>> 
>> xe3p_lpd_fbc_update_sys_cache_usage() is the function that should
>> check
>> for HAS_FBC_SYS_CACHE() in one place.
>> 
>> Well, maybe it should be renamed fbc_sys_cache_enable().
>> 
>> >  }
>> >  
>> >  /**
>> > @@ -2212,6 +2298,9 @@ void intel_fbc_init(struct intel_display
>> > *display)
>> >  
>> >  	for_each_fbc_id(display, fbc_id)
>> >  		display->fbc.instances[fbc_id] =
>> > intel_fbc_create(display, fbc_id);
>> > +
>> > +	/* Mark that no FBC instance is using the system cache */
>> > +	xe3p_lpd_fbc_set_sys_cache_fbc_id(display,
>> > SYS_CACHE_FBC_INSTANCE_NONE);
>> >  }
>> >  
>> >  /**
>> > @@ -2231,6 +2320,10 @@ void intel_fbc_sanitize(struct intel_display
>> > *display)
>> >  		if (intel_fbc_hw_is_active(fbc))
>> >  			intel_fbc_hw_deactivate(fbc);
>> >  	}
>> > +
>> > +	/* Ensure the sys cache usage register gets cleared */
>> > +	if (HAS_FBC_SYS_CACHE(display))
>> > +		xe3p_lpd_fbc_clear_sys_cache_usage(display);
>> 
>> Ditto about checking for valid sys cache inside, not
>> HAS_FBC_SYS_CACHE().
>> 
>> >  }
>> >  
>> >  static int intel_fbc_debugfs_status_show(struct seq_file *m, void
>> > *unused)
>> > diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > index b1d0161a3196..d2d889fa4bed 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
>> > @@ -126,4 +126,14 @@
>> >  #define   FBC_REND_NUKE			REG_BIT(2)
>> >  #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
>> >  
>> > +#define XE3P_LPD_FBC_SYS_CACHE_USAGE_CFG	_MMIO(0x1344E0)
>> > +#define  
>> > FBC_SYS_CACHE_START_BASE_MASK		REG_GENMASK(31, 16)
>> > +#define  
>> > FBC_SYS_CACHE_START_BASE(base)	REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK,(base))
>> > +#define   FBC_SYS_CACHEABLE_RANGE_MASK		REG_GENMASK(15, 4)
>> > +#define  
>> > FBC_SYS_CACHEABLE_RANGE(range)	REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK,(range))
>> > +#define   FBC_SYS_CACHE_TAG_MASK		REG_GENMASK(3, 2)
>> > +#define  
>> > FBC_SYS_CACHE_TAG_DONT_CACHE		REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,0)
>> > +#define  
>> > FBC_SYS_CACHE_TAG_USE_RES_SPACE	REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK,3)
>> > +#define   FBC_SYS_CACHE_READ_ENABLE		REG_BIT(0)
>> > +
>> >  #endif /* __INTEL_FBC_REGS__ */
>> 
>

-- 
Jani Nikula, Intel

Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Jani Nikula]

On Sun, 23 Nov 2025, Vinod Govindapillai <vinod.govindapillai@intel.com> wrote:
> One of the FBC instances can utilize the reserved area of SoC
> level cache for the fbc transactions to benefit reduced memory
> system power especially in idle scenarios. Reserved area of the
> system cache can be assigned to an fbc instance by configuring
> the cacheability configuration register with offset of the
> compressed frame buffer in stolen memoty of that fbc. There is
> a limit to this reserved area which is programmable and for
> xe3p_lpd the limit is defined as 2MB.
>
> v2: - better to track fbc sys cache usage from intel_display level,
>       sanitize the cacheability config register on probe (Matt)
>     - limit this for integrated graphics solutions, confirmed that
>       no default value set for cache range by hw (Gustavo)
>
> v3: - changes related to the use of fbc substruct in intel_display
>     - use intel_de_write() instead of intel_rmw() by hardcoding the
>       default value fields

Overall issue: The fbc mutexes are per fbc instance, but nothing
protects display->fbc.sys_cache_id.

BR,
Jani.


-- 
Jani Nikula, Intel

✓ i915.CI.BAT: success for drm/i915/display: Enable system cache support for FBC

[Patchwork]

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== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC
URL   : https://patchwork.freedesktop.org/series/157945/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17579 -> Patchwork_157945v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_157945v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-adlp-9:         [PASS][1] -> [ABORT][2] ([i915#14365]) +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-adlp-9/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/bat-adlp-9/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [DMESG-FAIL][3] ([i915#12061]) -> [PASS][4] +1 other test pass
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/bat-arls-5/igt@i915_selftest@live@workarounds.html
    - bat-dg2-9:          [DMESG-FAIL][5] ([i915#12061]) -> [PASS][6] +1 other test pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][7] ([i915#12061]) -> [PASS][8] +1 other test pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365


Build changes
-------------

  * Linux: CI_DRM_17579 -> Patchwork_157945v1

  CI-20190529: 20190529
  CI_DRM_17579: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157945v1: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/index.html

[-- Attachment #2: Type: text/html, Size: 3528 bytes --]

✗ i915.CI.Full: failure for drm/i915/display: Enable system cache support for FBC

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 65487 bytes --]

== Series Details ==

Series: drm/i915/display: Enable system cache support for FBC
URL   : https://patchwork.freedesktop.org/series/157945/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17579_full -> Patchwork_157945v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_157945v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_157945v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_157945v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_ctx_isolation@preservation-s3:
    - shard-tglu-1:       NOTRUN -> [ABORT][1] +2 other tests abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@gem_ctx_isolation@preservation-s3.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-mtlp:         [PASS][2] -> [ABORT][3] +4 other tests abort
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-3/igt@gem_exec_suspend@basic-s0.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-mtlp-5/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_softpin@noreloc-s3:
    - shard-dg2:          [PASS][4] -> [ABORT][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-7/igt@gem_softpin@noreloc-s3.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-8/igt@gem_softpin@noreloc-s3.html

  * igt@gem_workarounds@suspend-resume:
    - shard-tglu:         [PASS][6] -> [ABORT][7] +1 other test abort
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-tglu-3/igt@gem_workarounds@suspend-resume.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-9/igt@gem_workarounds@suspend-resume.html
    - shard-glk10:        NOTRUN -> [ABORT][8] +3 other tests abort
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk10/igt@gem_workarounds@suspend-resume.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-tglu:         NOTRUN -> [ABORT][9]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-snb:          [PASS][10] -> [ABORT][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-snb6/igt@i915_suspend@basic-s3-without-i915.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-snb5/igt@i915_suspend@basic-s3-without-i915.html
    - shard-dg1:          [PASS][12] -> [ABORT][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg1-12/igt@i915_suspend@basic-s3-without-i915.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg1-18/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3:
    - shard-dg1:          NOTRUN -> [ABORT][14] +3 other tests abort
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg1-12/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a3.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [ABORT][15] +2 other tests abort
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-4/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][16] +1 other test abort
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-7/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-b-hdmi-a-1:
    - shard-snb:          NOTRUN -> [ABORT][17]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-snb5/igt@kms_vblank@ts-continuation-suspend@pipe-b-hdmi-a-1.html

  
#### Warnings ####

  * igt@i915_suspend@debugfs-reader:
    - shard-glk:          [INCOMPLETE][18] ([i915#4817]) -> [ABORT][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk6/igt@i915_suspend@debugfs-reader.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk1/igt@i915_suspend@debugfs-reader.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-mtlp:         [INCOMPLETE][20] ([i915#13026]) -> [ABORT][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-mtlp-2/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  
New tests
---------

  New tests have been introduced between CI_DRM_17579_full and Patchwork_157945v1_full:

### New IGT tests (6) ###

  * igt@gem_lmem_evict@dontneed-evict-race:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_pm_rps@fbc-1p-primscrn-shrfb-pgflip-blt:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_pm_rps@seamless-rr-switch-virtual:
    - Statuses :
    - Exec time: [None] s

  * igt@i915_pm_rps@wait-forked-busy:
    - Statuses :
    - Exec time: [None] s

  * igt@kms_feature_discovery@display-1x:
    - Statuses :
    - Exec time: [None] s

  * igt@syncobj_wait@wait-zero-handles:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  

Known issues
------------

  Here are the changes found in Patchwork_157945v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-tglu-1:       NOTRUN -> [SKIP][22] ([i915#3555] / [i915#9323])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-tglu:         NOTRUN -> [SKIP][23] ([i915#9323])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-tglu:         NOTRUN -> [SKIP][24] ([i915#280])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@hibernate:
    - shard-tglu:         NOTRUN -> [ABORT][25] ([i915#7975])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@gem_eio@hibernate.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-tglu:         NOTRUN -> [SKIP][26] ([i915#4525])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][27] ([i915#4613])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][28] ([i915#4613]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-tglu-1:       NOTRUN -> [SKIP][29] ([i915#4613]) +1 other test skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_pread@self:
    - shard-rkl:          NOTRUN -> [SKIP][30] ([i915#3282])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@gem_pread@self.html

  * igt@gem_userptr_blits@readonly-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][31] ([i915#3297])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gem_userptr_blits@readonly-unsync.html

  * igt@gen7_exec_parse@load-register-reg:
    - shard-tglu:         NOTRUN -> [SKIP][32] +22 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gen7_exec_parse@load-register-reg.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-tglu-1:       NOTRUN -> [SKIP][33] ([i915#2527] / [i915#2856])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-rkl:          NOTRUN -> [SKIP][34] ([i915#2527])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-tglu:         NOTRUN -> [SKIP][35] ([i915#2527] / [i915#2856])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-tglu:         NOTRUN -> [SKIP][36] ([i915#6590]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [PASS][37] -> [INCOMPLETE][38] ([i915#13729] / [i915#13821])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-snb1/igt@i915_pm_rps@reset.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-snb7/igt@i915_pm_rps@reset.html

  * igt@i915_selftest@live@workarounds:
    - shard-dg2:          [PASS][39] -> [DMESG-FAIL][40] ([i915#12061]) +1 other test dmesg-fail
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-5/igt@i915_selftest@live@workarounds.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-11/igt@i915_selftest@live@workarounds.html

  * igt@intel_hwmon@hwmon-write:
    - shard-tglu:         NOTRUN -> [SKIP][41] ([i915#7707])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@intel_hwmon@hwmon-write.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][42] ([i915#5286]) +2 other tests skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][43] ([i915#5286]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [PASS][44] -> [FAIL][45] ([i915#5138])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][46] +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][47] ([i915#10307] / [i915#6095]) +49 other tests skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-1/igt@kms_ccs@bad-aux-stride-yf-tiled-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][48] ([i915#14098] / [i915#6095]) +22 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-4/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][49] ([i915#6095]) +43 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-7/igt@kms_ccs@ccs-on-another-bo-yf-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#12313])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][51] ([i915#6095]) +35 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg1-18/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-4.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#12313])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#6095]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-4/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][54] ([i915#12796] / [i915#14694]) +1 other test incomplete
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk3/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#14544] / [i915#6095]) +3 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][56] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][57] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][58] ([i915#6095]) +19 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
    - shard-tglu:         NOTRUN -> [SKIP][59] ([i915#6095]) +34 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][60] ([i915#13781]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_audio@dp-audio-edid:
    - shard-tglu-1:       NOTRUN -> [SKIP][61] ([i915#11151] / [i915#7828]) +2 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_chamelium_audio@dp-audio-edid.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#11151] / [i915#7828])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-tglu:         NOTRUN -> [SKIP][63] ([i915#11151] / [i915#7828]) +4 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][64] ([i915#7173])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-3.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][65] ([i915#3116] / [i915#3299])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][66] ([i915#6944] / [i915#9424])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@lic-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][67] ([i915#6944] / [i915#9424])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_content_protection@lic-type-1.html

  * igt@kms_cursor_crc@cursor-offscreen-max-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][68] ([i915#3555]) +1 other test skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-max-size.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#3555])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#3555])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-tglu:         NOTRUN -> [SKIP][71] ([i915#13049])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-rkl:          [PASS][72] -> [FAIL][73] ([i915#13566])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-7/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][74] ([i915#13566])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-256x85@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][75] ([i915#12358] / [i915#14152] / [i915#7882])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk1/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][76] ([i915#12358] / [i915#14152])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk1/igt@kms_cursor_crc@cursor-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-tglu:         NOTRUN -> [SKIP][77] ([i915#9067])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][78] ([i915#3804])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-tglu:         NOTRUN -> [SKIP][79] ([i915#13749])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dsc@dsc-with-bpc-formats:
    - shard-tglu:         NOTRUN -> [SKIP][80] ([i915#3555] / [i915#3840])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_dsc@dsc-with-bpc-formats.html

  * igt@kms_feature_discovery@display-2x:
    - shard-tglu-1:       NOTRUN -> [SKIP][81] ([i915#1839])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][82] ([i915#9934]) +3 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-glk10:        NOTRUN -> [SKIP][83] +75 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk10/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-nonexisting-fb-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#3637] / [i915#9934]) +4 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_flip@2x-nonexisting-fb-interruptible.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][85] ([i915#3637] / [i915#9934]) +2 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#2587] / [i915#2672]) +3 other tests skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][87] ([i915#2587] / [i915#2672] / [i915#3555])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][88] ([i915#2587] / [i915#2672])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][89] ([i915#2672] / [i915#3555])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#2672])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][91] ([i915#2672] / [i915#3555]) +3 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][92] +20 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#1825]) +8 other tests skip
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][94] ([i915#15102]) +6 other tests skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw:
    - shard-rkl:          NOTRUN -> [SKIP][95] ([i915#15102] / [i915#3023]) +2 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-tglu:         NOTRUN -> [SKIP][96] ([i915#15102]) +13 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [PASS][97] -> [SKIP][98] ([i915#3555] / [i915#8228])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_hdr@static-toggle.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-1/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][99] ([i915#3555] / [i915#8228])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][100] ([i915#12339])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#10656])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [PASS][102] -> [SKIP][103] ([i915#10656] / [i915#12388])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-1/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][104] ([i915#1839] / [i915#4816])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][105] ([i915#13476])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-7/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-b-hdmi-a-2.html

  * igt@kms_pipe_stress@stress-xrgb8888-4tiled:
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#14712])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][107] ([i915#13026]) +1 other test incomplete
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk5/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-tglu-1:       NOTRUN -> [SKIP][108] ([i915#13958])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][109] ([i915#12247]) +9 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#8430])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-tglu:         NOTRUN -> [SKIP][111] ([i915#6524])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#11520]) +2 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#11520])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-glk10:        NOTRUN -> [SKIP][114] ([i915#11520]) +1 other test skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk10/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][115] ([i915#11520]) +1 other test skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][116] ([i915#11520])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk3/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#9683])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-tglu:         NOTRUN -> [SKIP][118] ([i915#9732]) +8 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@fbc-psr-sprite-plane-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#1072] / [i915#9732]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_psr@fbc-psr-sprite-plane-onoff.html

  * igt@kms_psr@fbc-psr2-sprite-mmap-gtt:
    - shard-tglu-1:       NOTRUN -> [SKIP][120] ([i915#9732]) +5 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_psr@fbc-psr2-sprite-mmap-gtt.html

  * igt@kms_psr@psr2-dpms:
    - shard-glk:          NOTRUN -> [SKIP][121] +16 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk3/igt@kms_psr@psr2-dpms.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][122] ([i915#9685])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][123] ([i915#5289])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_sharpness_filter@filter-scaler-upscale:
    - shard-tglu:         NOTRUN -> [SKIP][124] ([i915#15232]) +2 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-5/igt@kms_sharpness_filter@filter-scaler-upscale.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][125] ([i915#12276])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-2.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][126] ([i915#12276])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-c-hdmi-a-2.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#9906])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-tglu-1:       NOTRUN -> [SKIP][128] ([i915#9906])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-tglu-1:       NOTRUN -> [SKIP][129] ([i915#2437] / [i915#9412])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-1/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-mtlp:         [ABORT][130] -> [PASS][131] +1 other test pass
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-mtlp-8/igt@gem_ctx_isolation@preservation-s3@rcs0.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-mtlp-6/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-tglu:         [ABORT][132] -> [PASS][133] +1 other test pass
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-tglu-6/igt@gem_exec_suspend@basic-s0@smem.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-tglu-6/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_softpin@noreloc-s3:
    - shard-dg1:          [ABORT][134] -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg1-14/igt@gem_softpin@noreloc-s3.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg1-15/igt@gem_softpin@noreloc-s3.html

  * igt@i915_suspend@basic-s2idle-without-i915:
    - shard-rkl:          [ABORT][136] -> [PASS][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-3/igt@i915_suspend@basic-s2idle-without-i915.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-3/igt@i915_suspend@basic-s2idle-without-i915.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          [SKIP][138] ([i915#3555]) -> [PASS][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-6/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
    - shard-dg2:          [FAIL][140] ([i915#6880]) -> [PASS][141]
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt.html

  * igt@kms_hdr@static-toggle:
    - shard-rkl:          [SKIP][142] ([i915#3555] / [i915#8228]) -> [PASS][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-5/igt@kms_hdr@static-toggle.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-1/igt@kms_hdr@static-toggle.html

  * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b:
    - shard-rkl:          [INCOMPLETE][144] ([i915#14412]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][146] ([i915#15073]) -> [PASS][147]
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          [ABORT][148] -> [PASS][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk6/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1:
    - shard-snb:          [ABORT][150] -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-snb7/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-snb5/igt@kms_vblank@ts-continuation-suspend@pipe-a-hdmi-a-1.html

  
#### Warnings ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          [SKIP][152] ([i915#14544] / [i915#8411]) -> [SKIP][153] ([i915#8411])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@api_intel_bb@object-reloc-purge-cache.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          [ABORT][154] -> [INCOMPLETE][155] ([i915#13356]) +1 other test incomplete
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@gem_exec_suspend@basic-s0@smem.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-7/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-rkl:          [SKIP][156] ([i915#14544] / [i915#4613]) -> [SKIP][157] ([i915#4613])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gem_lmem_swapping@parallel-random.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_madvise@dontneed-before-pwrite:
    - shard-rkl:          [SKIP][158] ([i915#14544] / [i915#3282]) -> [SKIP][159] ([i915#3282])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gem_madvise@dontneed-before-pwrite.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@gem_madvise@dontneed-before-pwrite.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          [SKIP][160] ([i915#8411]) -> [SKIP][161] ([i915#14544] / [i915#8411])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          [SKIP][162] ([i915#14544] / [i915#3297]) -> [SKIP][163] ([i915#3297])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-rkl:          [SKIP][164] ([i915#3297]) -> [SKIP][165] ([i915#14544] / [i915#3297])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-rkl:          [SKIP][166] ([i915#14544] / [i915#2527]) -> [SKIP][167] ([i915#2527])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@gen9_exec_parse@batch-invalid-length.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@i915_pm_freq_api@freq-suspend@gt0:
    - shard-dg2:          [ABORT][168] -> [INCOMPLETE][169] ([i915#13356] / [i915#13820]) +1 other test incomplete
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-8/igt@i915_pm_freq_api@freq-suspend@gt0.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-6/igt@i915_pm_freq_api@freq-suspend@gt0.html

  * igt@i915_power@sanity:
    - shard-rkl:          [SKIP][170] ([i915#7984]) -> [SKIP][171] ([i915#14544] / [i915#7984])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@i915_power@sanity.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@i915_power@sanity.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          [SKIP][172] ([i915#5723]) -> [SKIP][173] ([i915#14544] / [i915#5723])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@i915_query@test-query-geometry-subslices.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@i915_query@test-query-geometry-subslices.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-rkl:          [SKIP][174] ([i915#14544] / [i915#5286]) -> [SKIP][175] ([i915#5286])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][176] ([i915#5286]) -> [SKIP][177] ([i915#14544] / [i915#5286])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-rkl:          [SKIP][178] ([i915#3638]) -> [SKIP][179] ([i915#14544] / [i915#3638]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][180] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][181] ([i915#14098] / [i915#6095]) +2 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs:
    - shard-dg1:          [SKIP][182] ([i915#6095]) -> [SKIP][183] ([i915#4423] / [i915#6095]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg1-12/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg1-12/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][184] ([i915#14098] / [i915#6095]) -> [SKIP][185] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc.html
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition:
    - shard-rkl:          [SKIP][186] ([i915#3742]) -> [SKIP][187] ([i915#14544] / [i915#3742])
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_cdclk@mode-transition.html
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color@ctm-green-to-red:
    - shard-rkl:          [SKIP][188] -> [SKIP][189] ([i915#14544]) +3 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_chamelium_color@ctm-green-to-red.html
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_chamelium_color@ctm-green-to-red.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-rkl:          [SKIP][190] ([i915#11151] / [i915#7828]) -> [SKIP][191] ([i915#11151] / [i915#14544] / [i915#7828])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_chamelium_frames@hdmi-crc-multiple.html
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_frames@hdmi-crc-single:
    - shard-rkl:          [SKIP][192] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][193] ([i915#11151] / [i915#7828]) +2 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_chamelium_frames@hdmi-crc-single.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_chamelium_frames@hdmi-crc-single.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          [SKIP][194] ([i915#7118] / [i915#9424]) -> [FAIL][195] ([i915#7173])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-6/igt@kms_content_protection@atomic-dpms.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          [SKIP][196] ([i915#3116]) -> [SKIP][197] ([i915#14544] / [i915#3116])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_content_protection@dp-mst-lic-type-1.html
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          [FAIL][198] ([i915#7173]) -> [SKIP][199] ([i915#7118] / [i915#9424])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_content_protection@legacy.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          [FAIL][200] ([i915#7173]) -> [SKIP][201] ([i915#9424])
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-dg2-11/igt@kms_content_protection@lic-type-0.html
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-dg2-4/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-32x32:
    - shard-rkl:          [SKIP][202] ([i915#14544] / [i915#3555]) -> [SKIP][203] ([i915#3555])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-32x32.html
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_cursor_crc@cursor-offscreen-32x32.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-rkl:          [SKIP][204] ([i915#14544]) -> [SKIP][205] +2 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-rkl:          [SKIP][206] ([i915#14544] / [i915#3840]) -> [SKIP][207] ([i915#3840])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-rkl:          [SKIP][208] ([i915#9934]) -> [SKIP][209] ([i915#14544] / [i915#9934]) +2 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][210] ([i915#12745] / [i915#4839] / [i915#6113]) -> [INCOMPLETE][211] ([i915#12745] / [i915#4839])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk3/igt@kms_flip@2x-flip-vs-suspend.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk9/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][212] ([i915#4839] / [i915#6113]) -> [INCOMPLETE][213] ([i915#4839])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk3/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk9/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-rkl:          [SKIP][214] ([i915#14544] / [i915#9934]) -> [SKIP][215] ([i915#9934])
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-rkl:          [SKIP][216] ([i915#14544] / [i915#2672] / [i915#3555]) -> [SKIP][217] ([i915#2672] / [i915#3555])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          [SKIP][218] ([i915#14544] / [i915#2672]) -> [SKIP][219] ([i915#2672])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt:
    - shard-rkl:          [SKIP][220] ([i915#1825]) -> [SKIP][221] ([i915#14544] / [i915#1825]) +9 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][222] ([i915#14544] / [i915#1825]) -> [SKIP][223] ([i915#1825]) +4 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt:
    - shard-rkl:          [SKIP][224] ([i915#15102]) -> [SKIP][225] ([i915#14544] / [i915#15102]) +1 other test skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-rkl:          [SKIP][226] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][227] ([i915#15102] / [i915#3023]) +2 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-rkl:          [SKIP][228] ([i915#12388]) -> [SKIP][229] ([i915#12388] / [i915#14544])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_joiner@basic-force-big-joiner.html
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          [SKIP][230] ([i915#6301]) -> [SKIP][231] ([i915#14544] / [i915#6301])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_panel_fitting@atomic-fastset.html
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-rkl:          [SKIP][232] ([i915#11520]) -> [SKIP][233] ([i915#11520] / [i915#14544])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][234] ([i915#11520] / [i915#14544]) -> [SKIP][235] ([i915#11520]) +1 other test skip
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_psr2_sf@pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr-sprite-blt:
    - shard-rkl:          [SKIP][236] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][237] ([i915#1072] / [i915#9732]) +3 other tests skip
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_psr@fbc-psr-sprite-blt.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_psr@fbc-psr-sprite-blt.html

  * igt@kms_psr@psr2-cursor-plane-move:
    - shard-rkl:          [SKIP][238] ([i915#1072] / [i915#9732]) -> [SKIP][239] ([i915#1072] / [i915#14544] / [i915#9732]) +2 other tests skip
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_psr@psr2-cursor-plane-move.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_psr@psr2-cursor-plane-move.html

  * igt@kms_sharpness_filter@filter-scaler-downscale:
    - shard-rkl:          [SKIP][240] ([i915#14544] / [i915#15232]) -> [SKIP][241] ([i915#15232])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@kms_sharpness_filter@filter-scaler-downscale.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@kms_sharpness_filter@filter-scaler-downscale.html

  * igt@kms_sharpness_filter@invalid-filter-with-scaler:
    - shard-rkl:          [SKIP][242] ([i915#15232]) -> [SKIP][243] ([i915#14544] / [i915#15232])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-2/igt@kms_sharpness_filter@invalid-filter-with-scaler.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-6/igt@kms_sharpness_filter@invalid-filter-with-scaler.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-glk:          [ABORT][244] -> [INCOMPLETE][245] ([i915#12276])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-glk6/igt@kms_vblank@ts-continuation-dpms-suspend.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-glk1/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          [SKIP][246] ([i915#14544] / [i915#9917]) -> [SKIP][247] ([i915#9917])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17579/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/shard-rkl-5/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12358]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12358
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12796]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12796
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13820
  [i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14152
  [i915#14412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14412
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14694]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14694
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15232]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15232
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7882]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7882
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_17579 -> Patchwork_157945v1

  CI-20190529: 20190529
  CI_DRM_17579: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8636: 254cd102396ff95d61f2ebe49fc09128878bf483 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_157945v1: ed157ca0caebebe3af6d38ca0fb64a403c84ce77 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_157945v1/index.html

[-- Attachment #2: Type: text/html, Size: 85548 bytes --]

Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Govindapillai, Vinod]

On Mon, 2025-11-24 at 18:25 +0200, Jani Nikula wrote:
> On Sun, 23 Nov 2025, Vinod Govindapillai
> <vinod.govindapillai@intel.com> wrote:
> > One of the FBC instances can utilize the reserved area of SoC
> > level cache for the fbc transactions to benefit reduced memory
> > system power especially in idle scenarios. Reserved area of the
> > system cache can be assigned to an fbc instance by configuring
> > the cacheability configuration register with offset of the
> > compressed frame buffer in stolen memoty of that fbc. There is
> > a limit to this reserved area which is programmable and for
> > xe3p_lpd the limit is defined as 2MB.
> > 
> > v2: - better to track fbc sys cache usage from intel_display level,
> >       sanitize the cacheability config register on probe (Matt)
> >     - limit this for integrated graphics solutions, confirmed that
> >       no default value set for cache range by hw (Gustavo)
> > 
> > v3: - changes related to the use of fbc substruct in intel_display
> >     - use intel_de_write() instead of intel_rmw() by hardcoding the
> >       default value fields
> 
> Overall issue: The fbc mutexes are per fbc instance, but nothing
> protects display->fbc.sys_cache_id.

The places where this sys_cache_id can be changed to a valid fbc
instance id + fbc cfb offset are protected by the fbc mutex as part of
intel_fbc_enable and intel_fbc_disable. That's is what I was mentioning
in my prev reply. And the places where this sys cache usage register
reset happens is outside the fbc context - where sanitize and remove
module gets called. I don't see a need to update the fbc.sys_cache_id
from anywhere else.

BR
Vinod

> 
> BR,
> Jani.
> 
> 

Re: [PATCH v3 2/2] drm/i915/xe3p_lpd: Enable display use of system cache for FBC

[Jani Nikula]

On Tue, 25 Nov 2025, "Govindapillai, Vinod" <vinod.govindapillai@intel.com> wrote:
> On Mon, 2025-11-24 at 18:25 +0200, Jani Nikula wrote:
>> On Sun, 23 Nov 2025, Vinod Govindapillai
>> <vinod.govindapillai@intel.com> wrote:
>> > One of the FBC instances can utilize the reserved area of SoC
>> > level cache for the fbc transactions to benefit reduced memory
>> > system power especially in idle scenarios. Reserved area of the
>> > system cache can be assigned to an fbc instance by configuring
>> > the cacheability configuration register with offset of the
>> > compressed frame buffer in stolen memoty of that fbc. There is
>> > a limit to this reserved area which is programmable and for
>> > xe3p_lpd the limit is defined as 2MB.
>> > 
>> > v2: - better to track fbc sys cache usage from intel_display level,
>> >       sanitize the cacheability config register on probe (Matt)
>> >     - limit this for integrated graphics solutions, confirmed that
>> >       no default value set for cache range by hw (Gustavo)
>> > 
>> > v3: - changes related to the use of fbc substruct in intel_display
>> >     - use intel_de_write() instead of intel_rmw() by hardcoding the
>> >       default value fields
>> 
>> Overall issue: The fbc mutexes are per fbc instance, but nothing
>> protects display->fbc.sys_cache_id.
>
> The places where this sys_cache_id can be changed to a valid fbc
> instance id + fbc cfb offset are protected by the fbc mutex as part of
> intel_fbc_enable and intel_fbc_disable. That's is what I was mentioning
> in my prev reply. And the places where this sys cache usage register
> reset happens is outside the fbc context - where sanitize and remove
> module gets called. I don't see a need to update the fbc.sys_cache_id
> from anywhere else.

That's not the point. Each FBC instance has its own mutex. Two FBC
instance mutexes could be held at the same time. I don't think this is
the case during enable/disable, though. But the point remains, the
instance mutex can't protect something that's not part of the instance.

BR,
Jani.


-- 
Jani Nikula, Intel