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[108.49.102.102]) by smtp.gmail.com with ESMTPSA id x25sm2458938qtj.77.2021.08.26.12.41.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Aug 2021 12:41:06 -0700 (PDT) Message-ID: <76e484cc5146e2ffd63aecff1e6bdb2803a772a0.camel@redhat.com> From: Lyude Paul To: Jani Nikula , Ville =?ISO-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Manasi Navare Date: Thu, 26 Aug 2021 15:41:05 -0400 In-Reply-To: <87lf4ocvfn.fsf@intel.com> References: <87eeahegw0.fsf@intel.com> <87lf4ocvfn.fsf@intel.com> Organization: Red Hat User-Agent: Evolution 3.40.4 (3.40.4-1.fc34) MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=lyude@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Subject: Re: [Intel-gfx] [PATCH 2/4] drm/dp: use more of the extended receiver cap X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 2021-08-26 at 14:11 +0300, Jani Nikula wrote: > On Wed, 25 Aug 2021, Jani Nikula wrote: > > On Thu, 19 Aug 2021, Ville Syrjälä wrote: > > > On Fri, Aug 13, 2021 at 01:43:20PM +0300, Jani Nikula wrote: > > > > Extend the use of extended receiver cap at 0x2200 to cover > > > > MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation > > > > hides > > > > the DP 2.0 128b/132b channel encoding cap. > > > > > > > > Cc: Manasi Navare > > > > Signed-off-by: Jani Nikula > > > > --- > > > >  drivers/gpu/drm/drm_dp_helper.c | 2 +- > > > >  1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/drivers/gpu/drm/drm_dp_helper.c > > > > b/drivers/gpu/drm/drm_dp_helper.c > > > > index 9b2a2961fca8..9389f92cb944 100644 > > > > --- a/drivers/gpu/drm/drm_dp_helper.c > > > > +++ b/drivers/gpu/drm/drm_dp_helper.c > > > > @@ -608,7 +608,7 @@ static u8 drm_dp_downstream_port_count(const u8 > > > > dpcd[DP_RECEIVER_CAP_SIZE]) > > > >  static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, > > > >                                           u8 > > > > dpcd[DP_RECEIVER_CAP_SIZE]) > > > >  { > > > > -       u8 dpcd_ext[6]; > > > > +       u8 dpcd_ext[DP_MAIN_LINK_CHANNEL_CODING + 1]; > > > > > > Why are we even reading less of this than the normal receiver caps? > > > > Good question. I forget my reasoning to only extend to what might affect > > this use case. Should we extend to the size of the usual receiver caps? > > Ah, there was a previous discussion [1] with Lyude (Cc'd). Yeah - basically the problem is that we just need to make sure we take care to avoid clearing info from the non-extended DPCD by accident. Extending this to 7 bits should be fine. JFYI reading back at your comments it sounds like we might actually be safe to read the entire DPCD, but we need to make sure we take care to avoid accidentally replacing the main DPCD with a zeroed-out DPCD which could happen on systems that have no support for extended DPCDs. (Also - super bonus points if you can write a unit test to confirm we're not overwriting the original DPCD! I don't know how much effort this would be though so don't worry about it too much) > > BR, > Jani. > > > [1] > https://patchwork.freedesktop.org/patch/msgid/20200901123226.4177-1-jani.nikula@intel.com > > > > > > BR, > > Jani. > > > > > > > > > > >         int ret; > > > >   > > > >         /* > > > > -- > > > > 2.20.1 > -- Cheers, Lyude Paul (she/her) Software Engineer at Red Hat