From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Souza, Jose" Subject: Re: [PATCH] drm/i915: FBC needs vblank before enable / disable. Date: Wed, 3 Apr 2019 17:54:49 +0000 Message-ID: <7eeff63f7536703ef72bdfa92c6e8ad6a4de9b5a.camel@intel.com> References: <1554265825-31346-1-git-send-email-kiran.s.kumar@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============2049011544==" Return-path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id B59CF6E91C for ; Wed, 3 Apr 2019 17:54:52 +0000 (UTC) In-Reply-To: <1554265825-31346-1-git-send-email-kiran.s.kumar@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "intel-gfx@lists.freedesktop.org" , "Kumar, Kiran S" List-Id: intel-gfx@lists.freedesktop.org --===============2049011544== Content-Language: en-US Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="=-nNwDgpndayVOYBTTjIat" --=-nNwDgpndayVOYBTTjIat Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, 2019-04-03 at 10:00 +0530, kiran.s.kumar@intel.com wrote: > From: Kiran Kumar S >=20 > As per the display workaround #1200, FBC needs wait for vblank before > enabling and before disabling FBC. >=20 > In some cases, depending on whether FBC was compressing in that > frame, > several control signals in the compression engine also will fail to > properly > recognize the final segment of the frame as a result of the missing > last > pixel indication. As a result of this, we're seeing corrupted cache > line/compression indicators after FBC re-enables which causes > underruns or > corruption when they're used to decompress. >=20 > WA sequence as below: > 1) Display enables plane 1A > 2) Wait for 1 vblank > 3) FBC gets enabled > 4) Wait for 1 VBLANK > 5) Turn off FBC >=20 > In GLK Chrome OS, if FBC is enabled by default, few top lines on the > screen > got corrupted. With the above WA, issue was resolved. >=20 > Change-Id: I2465610bb0a82df99e5c53b1eb4ed74565996b1e > Signed-off-by: Kiran Kumar S < > kiran.s.kumar@intel.corp-partner.google.com> > --- > drivers/gpu/drm/i915/intel_display.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 8576a7f799f2..5118a36782eb 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -13207,8 +13207,11 @@ static void intel_update_crtc(struct > drm_crtc *crtc, > =20 > if (pipe_config->update_pipe && !pipe_config->enable_fbc) > intel_fbc_disable(intel_crtc); > - else if (new_plane_state) > + else if (new_plane_state) { > + /* Display WA #1200: GLK */ > + intel_wait_for_vblank(dev_priv, intel_crtc->pipe); Wait a vblank of partially changed state? That is not a good idea at all. Also it would wait a vblank even if FBC is not enabled. > intel_fbc_enable(intel_crtc, pipe_config, > new_plane_state); > + } > =20 > intel_begin_crtc_commit(crtc, old_crtc_state); > =20 > @@ -13419,6 +13422,8 @@ static void intel_atomic_commit_tail(struct > drm_atomic_state *state) > =20 > dev_priv- > >display.crtc_disable(old_intel_crtc_state, state); > intel_crtc->active =3D false; > + /* Display WA #1200: GLK */ > + intel_wait_for_vblank(dev_priv, intel_crtc- > >pipe); > intel_fbc_disable(intel_crtc); > intel_disable_shared_dpll(old_intel_crtc_state) > ; > =20 --=-nNwDgpndayVOYBTTjIat Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part Content-Transfer-Encoding: 7bit -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEVNG051EijGa0MiaQVenbO/mOWkkFAlyk82kACgkQVenbO/mO Wkl4zwf/U7JAZTlt/V7FoKRJWOojYexGGsiwDRQ0yWZK+BfcB+7wQg1Y9OCYlCLH EDeu/kMPOZ41SSNv0DVKbwtdlX3feVCu1o2ATw9K+I+L1D/weEARPaHTYaYlEow3 usyVnzyLvbSLK+wEblfglg/j4z6i0J507iVa9roD50YaZBhd1XNTZZII6quUNO0O E0jzqVNxiboUN4ul1vhDQM8tsaNPzNQegNNrIowBJGcACD/Emae8Rerh2eey2sp+ LYoVOk7qEWBG9yH/Aq/6+ZIZ4Bu7i+oM4ENBdRtp2Sm7MsyX4adowSylnzK9c9hC 7APIGXbpaij6oknPvHArU/bEYWxeLQ== =g+jI -----END PGP SIGNATURE----- --=-nNwDgpndayVOYBTTjIat-- --===============2049011544== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4 --===============2049011544==--