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Content-Language: en-US To: Mitul Golani , CC: References: <20240222121223.2257958-1-mitulkumar.ajitkumar.golani@intel.com> <20240222121223.2257958-5-mitulkumar.ajitkumar.golani@intel.com> From: "Nautiyal, Ankit K" In-Reply-To: <20240222121223.2257958-5-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: PN2PR01CA0214.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:ea::9) To DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM4PR11MB5341:EE_|BL1PR11MB5493:EE_ X-MS-Office365-Filtering-Correlation-Id: f26651ea-4b11-48f3-a6c2-08dc36b11b10 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6779DjvJvtMJjVUIH8T99DEVoi0E3rysuqyVtAKQnsYf0RRDDLhOX0E08qLc0C6Usq5TqDJ9DY9EWZ/Rv+TwBQ3ukyOUtZ/Zzb9w5JZI0JZFonoR5tasbH5OYOvRhH0ZkXSAUOnDVq+IylfxsteD+XzTTlg6iOW25Rt5kbAVrOMQ7u45sF9rXRVIFBcnReWE3dnLogOqbONw9+LW1Vqke+YpbJg8N32LtrLwmlUY31PNSJZf76x58WekfiCMoWA0zoCbWTywilFf4jkbWsN75ojiIbgie93NI32hG1qmVZSnts6hlxAfPqokr0Dy4dfIVCaEI6ZgBgmNRp7CO4FHPfm7qTxj2fRvwyHXGMJPu2PGZegzRKokHJbvUZ35BHrX1zY/NH8My3io2K3Oh+8JGu7j/d27wprdS328rrqS0TyI0m8axTQaUVZEykSNg5nm4fNiJ19NmV95JIAQIEMetQ4X7KGHDHtNp/bDRUd3d46XY8Cz6m6pZMp51ZxguRFrnQr3BhzI+0nRxL2Irr9DnDzZylU8iKTvZKx4gumA9kIvml29sNdSCb0+YhTm0lBkKKb0/RTtCfqaeDy47YPUF3P9YP7F8tj+SZM/4X55KL015apixHlBFJ5+Uoub1oDhaelK671sUqFeKXiuGYAAVw== X-Forefront-Antispam-Report: CIP:255.255.255.255; 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The new `intel_dp_compute_as_sdp` > function computes AS SDP values based on the display > configuration, ensuring proper handling of Variable Refresh > Rate (VRR). > > --v2: > - Add DP_SDP_ADAPTIVE_SYNC to infoframe_type_to_idx().[Ankit] > - separate patch for intel_read/write_dp_sdp [Ankit]. > - _HSW_VIDEO_DIP_ASYNC_DATA_A should be from ADL onward [Ankit] > - To fix indentation [Ankit] > > --v3: > - Add VIDEO_DIP_ENABLE_AS_HSW flag to intel_dp_set_infoframes. > > --v4: > - Add HAS_VRR check before write as sdp. > > --v5: > - Add missed HAS_VRR check before read as sdp. > > --v6: > Use Adaptive Sync sink status, which can be > used as a check for read/write sdp. (Ankit) > > Signed-off-by: Mitul Golani > --- > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 28 +++++++++++++++++++ > drivers/gpu/drm/i915/display/intel_vrr.c | 4 ++- > 3 files changed, 32 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 2accfe41160d..93b4b7dff1d0 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1415,6 +1415,7 @@ struct intel_crtc_state { > u8 pipeline_full; > u16 flipline, vmin, vmax, guardband; > u8 as_sdp_mode; > + bool as_sdp_enable; This is again specific to DP, we can do away with this in vrr struct. > } vrr; > > /* Stream Splitter for eDP MSO */ > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index b370e1da4735..5c1e2301dd52 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2617,6 +2617,33 @@ static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc > vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; > } > > +static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, > + struct intel_crtc_state *crtc_state, > + const struct drm_connector_state *conn_state) > +{ > + struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp; > + struct intel_connector *connector = intel_dp->attached_connector; > + const struct drm_display_mode *adjusted_mode = > + &crtc_state->hw.adjusted_mode; > + int vrefresh = drm_mode_vrefresh(adjusted_mode); > + > + if (!intel_vrr_is_in_range(connector, vrefresh) || !crtc_state->vrr.as_sdp_enable) > + return; > + > + as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; > + as_sdp->length = 0x9; > + as_sdp->mode = crtc_state->vrr.as_sdp_mode; > + as_sdp->vtotal = adjusted_mode->vtotal; > + > + if (as_sdp->mode == DP_AS_SDP_AVT_FIXED_VTOTAL) { Currently we are just supporting DP_AS_SDP_AVT_FIXED_VTOTAL so this check is not required. But we can add a comment mentioning the same. > + as_sdp->target_rr = 0; > + as_sdp->duration_incr_ms = 0; > + as_sdp->duration_incr_ms = 0; > + } > + > + crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC); > +} We will need to add this to state checker, something like PIPE_CONF_CHECK_DP_AS_SDP and add function to compare the adaptive sync sdp struct. Regards, Ankit > + > static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state, > const struct drm_connector_state *conn_state) > @@ -2942,6 +2969,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, > g4x_dp_set_clock(encoder, pipe_config); > > intel_vrr_compute_config(pipe_config, conn_state); > + intel_dp_compute_as_sdp(intel_dp, pipe_config, conn_state); > intel_psr_compute_config(intel_dp, pipe_config, conn_state); > intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); > intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index d2ab7e571e62..08e3ba69bd30 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -167,9 +167,11 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > crtc_state->vrr.enable = true; > crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > > - if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd)) > + if (drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd)) { > + crtc_state->vrr.as_sdp_enable = true; > crtc_state->vrr.as_sdp_mode = > DP_AS_SDP_AVT_DYNAMIC_VTOTAL; > + } > } > } >