From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [intel-gpu-tools][PATCH] Correct identification of the GEN5 chips on the IS_9XX() define Date: Mon, 14 Feb 2011 15:59:09 +0000 Message-ID: <849307$bignk4@azsmga001.ch.intel.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 6F58E9E798 for ; Mon, 14 Feb 2011 07:59:21 -0800 (PST) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Diego Celix , intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Mon, 14 Feb 2011 15:44:51 +0000, Diego Celix wrote: > Hi, > > I've been trying to find the main cause because I got the following error: > > Couldn't map MMIO region: No such file or directory Sigh. I wrote that off as another bug, since it was exactly the same symptom as when changing the caching mode of the registers. I applied a variant of that patch to remove IS_9XX instead. -Chris -- Chris Wilson, Intel Open Source Technology Centre