From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 6/8] drm/i915: change force wake order for GT read Date: Tue, 22 Mar 2011 07:25:02 +0000 Message-ID: <849307$c3dlsf@azsmga001.ch.intel.com> References: <1300699639-23996-1-git-send-email-zhenyuw@linux.intel.com> <1300699639-23996-7-git-send-email-zhenyuw@linux.intel.com> <1bdc18$jud1l6@fmsmga002.fm.intel.com> <20110322012751.GI27541@zhen-devel.sh.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id BEC159E747 for ; Tue, 22 Mar 2011 00:25:05 -0700 (PDT) In-Reply-To: <20110322012751.GI27541@zhen-devel.sh.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Zhenyu Wang Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, 22 Mar 2011 09:27:51 +0800, Zhenyu Wang wrote: > Just mean to follow the doc, it matches the sequence of RC6 enabling steps > from GT PM programming doc, not sure if it's strictly required. But as you point out, the docs do also outline the current method as well. ;-) Meanwhile a better solution for _gen6_gt_wait_for_fifo() is desperately sought. It is the new clflush. [Ok, most of that could be mitigated by improving the ddx...] -Chris -- Chris Wilson, Intel Open Source Technology Centre