[PATCH 1/8] drm/i915: clock gating fix for gen5 and gen6

Zhenyu Wang
2011-03-21T09:27:21Z

Some bits should only be set when enable FBC.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++-
drivers/gpu/drm/i915/intel_display.c | 27 ++++++++++++++-------------
2 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2abe240..b0aabe4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2771,8 +2771,10 @@
#define ILK_eDP_A_DISABLE (1<<24)
#define ILK_DESKTOP (1<<23)
#define ILK_DSPCLK_GATE 0x42020
-#define ILK_DPARB_CLK_GATE (1<<5)
+#define ILK_DPFC_CLK_GATE (1<<9)
+#define ILK_DPFCR_CLK_GATE (1<<8)
#define ILK_DPFD_CLK_GATE (1<<7)
+#define ILK_DPARB_CLK_GATE (1<<5)

/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
#define ILK_CLK_FBC (1<<7)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 232c4ec..13b17e0 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6461,7 +6461,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
ILK_FBCQ_DIS);
I915_WRITE(ILK_DISPLAY_CHICKEN2,
I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE);
+ ILK_DPARB_GATE | ILK_ELPIN_409_SELECT);
I915_WRITE(ILK_DSPCLK_GATE,
I915_READ(ILK_DSPCLK_GATE) |
ILK_DPFC_DIS1 |
@@ -6469,10 +6469,6 @@ void intel_enable_clock_gating(struct drm_device *dev)
ILK_CLK_FBC);
}

- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_ELPIN_409_SELECT);
-
if (IS_GEN5(dev)) {
I915_WRITE(_3D_CHICKEN2,
_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
@@ -6493,16 +6489,21 @@ void intel_enable_clock_gating(struct drm_device *dev)
* The bit14 of 0x70180
* The bit14 of 0x71180
*/
- I915_WRITE(ILK_DISPLAY_CHICKEN1,
- I915_READ(ILK_DISPLAY_CHICKEN1) |
- ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+ if (I915_HAS_FBC(dev) && i915_powersave) {
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPFC_CLK_GATE | ILK_DPFCR_CLK_GATE);
+ } else
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_PABSTRETCH_DIS);
+
I915_WRITE(ILK_DISPLAY_CHICKEN2,
I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL);
- I915_WRITE(ILK_DSPCLK_GATE,
- I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPARB_CLK_GATE |
- ILK_DPFD_CLK_GATE);
+ ILK_VSDPFD_FULL | ILK_ELPIN_409_SELECT);

I915_WRITE(DSPACNTR,
I915_READ(DSPACNTR) |
--
1.7.4.1