From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 1/2] drm/i915/crt: Remove 0xa0 probe for CRT Date: Mon, 04 Apr 2011 16:29:55 +0100 Message-ID: <849307$cab831@azsmga001.ch.intel.com> References: <1301898405-6999-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id EADC19E79E for ; Mon, 4 Apr 2011 08:29:58 -0700 (PDT) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Keith Packard , intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, 04 Apr 2011 08:08:40 -0700, Keith Packard wrote: > On Mon, 4 Apr 2011 07:26:44 +0100, Chris Wilson wrote: > > > Following the fix to reset the GMBUS controller after a NAK, we finally > > utilize the 0xa0 probe for a CRT connection. And discover that it is > > useless as it simply detects the presence of the controller and not the > > actual monitor. Given that we already probe 0x50 prior to performing the > > EDID retrieval, we can simply remove the redundant probe to 0xa0. > > I don't understand -- are you saying that there is additional hardware > somewhere in the machine responding to I2C transactions on the monitor's > DDC bus? Yes. I'm saying that that the controller accepts a write to port 0xa0. > And if so, how was this extra transaction breaking things? The GMBUS > reset patch should only have an effect when there are failed > transactions, not successful ones, and then it should only cause future > transactions to fail, not succeed. Besides, the 0xA0 transaction looks > like the first one on the bus. We do several i2c xfers before CRT. -Chris -- Chris Wilson, Intel Open Source Technology Centre