From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [PATCH 21/30] drm/i915: Redirect GTT mappings to
	the CPU page if cache-coherent
Date: Wed, 13 Apr 2011 17:19:55 +0100
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To: Eric Anholt <eric@anholt.net>, intel-gfx@lists.freedesktop.org
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On Wed, 13 Apr 2011 08:57:01 -0700, Eric Anholt <eric@anholt.net> wrote:
> On Tue, 12 Apr 2011 21:31:49 +0100, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> > ... or if we will need to perform a cache-flush on the object anyway.
> > Unless, of course, we need to use a fence register to perform tiling
> > operations during the transfer.
> 
> Here's the case I see: I've GTT-map-written a BO (so it hit backing
> pages), then that object becomes the framebuffer (PTEs changed to
> uncached), then we try to GTT-map-write it some more.  The fake GTT map
> skips that.

Hmm, we missed a i915_gem_release_mmap in set_cache_level(). But otherwise
if we attempt to read an I915_CACHE_NONE object we do so through the GTT.

So:

set_cache_level(bo, CACHE_LLC);
ptr = mmap_gtt(bo);
*ptr --> pages are left in the CPU domain and read via the normal page.
set_cache_level(bo, CACHE_NONE); --> i915_gem_release_mmap(bo);
*ptr --> the pagefault handler is called again and now we return a UC page

 
> Also, looks like unrelated change to madvise?

No, it is related since the vma is populated outside of being bound by the
GTT now and so needs to be cleared along with truncate.  Deserves a comment
for being non-obvious.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre