From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: Set DERRMR around batches required vblank events Date: Wed, 29 Aug 2012 16:33:13 +0100 Message-ID: <84c8a8$5i2r5r@orsmga001.jf.intel.com> References: <1343334619-28340-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id C8C799ED63 for ; Wed, 29 Aug 2012 08:33:51 -0700 (PDT) In-Reply-To: <1343334619-28340-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, 26 Jul 2012 21:30:19 +0100, Chris Wilson wrote: > In order for the Display Engine to send messages to the Render Engine, > that event must be unmasked in the Display Engine Render Response Mask > Register (DERRMR). By default all events are masked to prevent unwanted > messages to conserve power, and it is strongly recommended that only > single events be unmasked at any time. So in order to pipeline the > register writes around individual batchbuffers, userspace must notify > the kernel when it requires a vblank event, this patch implements an > interface to do so with an single (pipe, event) request through the > execbuffer flags. > > Note that another workaround is required for IVB, in that we must also > prevent RC6 sleeps whilst waiting upon an event. To do that we also > pipeline a forcewake into the second MT slot. Anyone have any criticisms for this patch? -Chris -- Chris Wilson, Intel Open Source Technology Centre