* [PATCH 1/2] drm/i915: don't save/restore panel fitter registers
@ 2014-11-12 14:25 Jani Nikula
2014-11-12 14:25 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist ctl registers Jani Nikula
0 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2014-11-12 14:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
AFAICT i9xx_pfit_disable() on the GMCH display crtc disable path in
i9xx_crtc_disable() will always disable the panel fitter by writing 0 to
PFIT_CONTROL. The register save will always save/restore 0.
Move the PFIT_CONTROL and PFIT_PGM_RATIOS save/restore to UMS
code. While at it, save/restore them both under the same conditions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
UNTESTED! *grin*
---
drivers/gpu/drm/i915/i915_suspend.c | 10 ----------
drivers/gpu/drm/i915/i915_ums.c | 12 ++++++++++++
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 26b6bf9261ca..df2b7f18a679 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -208,23 +208,17 @@ static void i915_save_display(struct drm_device *dev)
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
} else if (IS_VALLEYVIEW(dev)) {
- dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
-
dev_priv->regfile.saveBLC_HIST_CTL =
I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
dev_priv->regfile.saveBLC_HIST_CTL_B =
I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
} else {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
- dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
if (IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->regfile.saveLVDS = I915_READ(LVDS);
}
- if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
- dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
-
if (HAS_PCH_SPLIT(dev)) {
dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
@@ -263,9 +257,6 @@ static void i915_restore_display(struct drm_device *dev)
else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
- if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
- I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
-
if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
@@ -277,7 +268,6 @@ static void i915_restore_display(struct drm_device *dev)
I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
dev_priv->regfile.saveBLC_HIST_CTL);
} else {
- I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 480da593e6c0..0e03c3610719 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -270,6 +270,12 @@ void i915_save_display_reg(struct drm_device *dev)
}
/* FIXME: regfile.save TV & SDVO state */
+ /* Panel fitter */
+ if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
+ dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
+ dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
+ }
+
/* Backlight */
if (INTEL_INFO(dev)->gen <= 4)
pci_read_config_byte(dev->pdev, PCI_LBPC,
@@ -315,6 +321,12 @@ void i915_restore_display_reg(struct drm_device *dev)
I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
}
+ /* Panel fitter */
+ if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
+ I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
+ I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
+ }
+
/* Display port ratios (must be done before clock is set) */
if (SUPPORTS_INTEGRATED_DP(dev)) {
I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
--
2.1.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] drm/i915: don't save/restore backlight hist ctl registers
2014-11-12 14:25 [PATCH 1/2] drm/i915: don't save/restore panel fitter registers Jani Nikula
@ 2014-11-12 14:25 ` Jani Nikula
2014-11-12 15:01 ` [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit Jani Nikula
2014-11-13 0:56 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist shuang.he
0 siblings, 2 replies; 7+ messages in thread
From: Jani Nikula @ 2014-11-12 14:25 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
This is not used within the driver, and merely saving/restoring these
registers isn't going to do any good anyway. In fact, it's possible it's
actively harmful. Any code enabling the feature should handle this
completely in the regular platform specific enable/disable backlight
functions.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
drivers/gpu/drm/i915/i915_suspend.c | 16 ++--------------
drivers/gpu/drm/i915/i915_ums.c | 2 ++
3 files changed, 4 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 45ca10937e3e..3f3035ce30e6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -799,7 +799,6 @@ struct i915_suspend_saved_registers {
u32 saveBLC_HIST_CTL;
u32 saveBLC_PWM_CTL;
u32 saveBLC_PWM_CTL2;
- u32 saveBLC_HIST_CTL_B;
u32 saveBLC_CPU_PWM_CTL;
u32 saveBLC_CPU_PWM_CTL2;
u32 saveFPB0;
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index df2b7f18a679..3c1fccfacac1 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -207,14 +207,8 @@ static void i915_save_display(struct drm_device *dev)
dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
- } else if (IS_VALLEYVIEW(dev)) {
- dev_priv->regfile.saveBLC_HIST_CTL =
- I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
- dev_priv->regfile.saveBLC_HIST_CTL_B =
- I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
- } else {
+ } else if (!IS_VALLEYVIEW(dev)) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
- dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
if (IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->regfile.saveLVDS = I915_READ(LVDS);
}
@@ -262,13 +256,7 @@ static void i915_restore_display(struct drm_device *dev)
I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
- } else if (IS_VALLEYVIEW(dev)) {
- I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
- dev_priv->regfile.saveBLC_HIST_CTL);
- I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
- dev_priv->regfile.saveBLC_HIST_CTL);
- } else {
- I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
+ } else if (!IS_VALLEYVIEW(dev)) {
I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 0e03c3610719..d10fe3e9c49f 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -290,6 +290,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
if (INTEL_INFO(dev)->gen >= 4)
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
+ dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
}
return;
@@ -319,6 +320,7 @@ void i915_restore_display_reg(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 4)
I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
+ I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
}
/* Panel fitter */
--
2.1.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit
2014-11-12 14:25 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist ctl registers Jani Nikula
@ 2014-11-12 15:01 ` Jani Nikula
2014-11-12 15:48 ` Daniel Vetter
2014-11-13 0:56 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist shuang.he
1 sibling, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2014-11-12 15:01 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, shuang.he
Use the same conditions, group by features, add comments.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_suspend.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 3c1fccfacac1..dfe661743398 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -203,21 +203,19 @@ static void i915_save_display(struct drm_device *dev)
i915_save_display_reg(dev);
/* LVDS state */
- if (HAS_PCH_SPLIT(dev)) {
- dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
- if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
- dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
- } else if (!IS_VALLEYVIEW(dev)) {
- dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
- if (IS_MOBILE(dev) && !IS_I830(dev))
- dev_priv->regfile.saveLVDS = I915_READ(LVDS);
- }
+ if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
+ dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
+ else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
+ dev_priv->regfile.saveLVDS = I915_READ(LVDS);
+ /* Panel power sequencer */
if (HAS_PCH_SPLIT(dev)) {
+ dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
} else if (!IS_VALLEYVIEW(dev)) {
+ dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
@@ -246,11 +244,13 @@ static void i915_restore_display(struct drm_device *dev)
if (drm_core_check_feature(dev, DRIVER_MODESET))
mask = ~LVDS_PORT_EN;
+ /* LVDS state */
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
+ /* Panel power sequencer */
if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
--
2.1.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit
2014-11-12 15:01 ` [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit Jani Nikula
@ 2014-11-12 15:48 ` Daniel Vetter
2014-11-13 7:19 ` Jani Nikula
0 siblings, 1 reply; 7+ messages in thread
From: Daniel Vetter @ 2014-11-12 15:48 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, shuang.he
On Wed, Nov 12, 2014 at 05:01:10PM +0200, Jani Nikula wrote:
> Use the same conditions, group by features, add comments.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_suspend.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 3c1fccfacac1..dfe661743398 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -203,21 +203,19 @@ static void i915_save_display(struct drm_device *dev)
> i915_save_display_reg(dev);
>
> /* LVDS state */
> - if (HAS_PCH_SPLIT(dev)) {
> - dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> - dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
> - } else if (!IS_VALLEYVIEW(dev)) {
> - dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
> - if (IS_MOBILE(dev) && !IS_I830(dev))
> - dev_priv->regfile.saveLVDS = I915_READ(LVDS);
> - }
> + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> + dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
> + else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
> + dev_priv->regfile.saveLVDS = I915_READ(LVDS);
>
> + /* Panel power sequencer */
> if (HAS_PCH_SPLIT(dev)) {
> + dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
> dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
> dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
> dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
> } else if (!IS_VALLEYVIEW(dev)) {
> + dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
> dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
> dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
> dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
Just because they're in the context: Do we still need to restore the PP
stuff with all the recent pps patches? Would be great to remove this ...
Anyway looks all good (and nicely frigthening ;-) so pulled all into dinq.
-Daniel
> @@ -246,11 +244,13 @@ static void i915_restore_display(struct drm_device *dev)
> if (drm_core_check_feature(dev, DRIVER_MODESET))
> mask = ~LVDS_PORT_EN;
>
> + /* LVDS state */
> if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
> I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
> else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
> I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
>
> + /* Panel power sequencer */
> if (HAS_PCH_SPLIT(dev)) {
> I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
> I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
> --
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] drm/i915: don't save/restore backlight hist
2014-11-12 14:25 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist ctl registers Jani Nikula
2014-11-12 15:01 ` [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit Jani Nikula
@ 2014-11-13 0:56 ` shuang.he
1 sibling, 0 replies; 7+ messages in thread
From: shuang.he @ 2014-11-13 0:56 UTC (permalink / raw)
To: shuang.he, intel-gfx, jani.nikula
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->291/291
PNV: pass/total=356/356->350/356
ILK: pass/total=372/372->364/372
IVB: pass/total=545/546->545/546
SNB: pass/total=380/380->379/380
HSW: pass/total=579/579->577/579
BDW: pass/total=434/435->434/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
PNV: Intel_gpu_tools, igt_gen3_mixed_blits, CRASH(1, M23)NRUN(2, M23)PASS(1, M25) -> CRASH(4, M23)
PNV: Intel_gpu_tools, igt_gen3_render_linear_blits, CRASH(3, M23)PASS(1, M25) -> CRASH(4, M23)
PNV: Intel_gpu_tools, igt_gen3_render_mixed_blits, CRASH(2, M23)NRUN(1, M23)PASS(1, M25) -> CRASH(3, M23)NRUN(1, M23)
PNV: Intel_gpu_tools, igt_gen3_render_tiledx_blits, CRASH(1, M23)NRUN(2, M23)PASS(1, M25) -> CRASH(3, M23)NRUN(1, M23)
PNV: Intel_gpu_tools, igt_gen3_render_tiledy_blits, CRASH(2, M23)NRUN(1, M23)PASS(1, M25) -> CRASH(3, M23)DMESG_WARN(1, M23)
PNV: Intel_gpu_tools, igt_kms_sysfs_edid_timing, FAIL(1, M23)PASS(3, M25M23) -> FAIL(1, M23)PASS(3, M23)
ILK: Intel_gpu_tools, igt_drv_suspend_fence-restore-untiled, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_bcs-wf_vblank-vs-dpms, DMESG_WARN(2, M26)PASS(2, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_bcs-wf_vblank-vs-dpms-interruptible, DMESG_WARN(3, M26)PASS(1, M26) -> DMESG_WARN(2, M26)PASS(2, M26)
ILK: Intel_gpu_tools, igt_kms_flip_flip-vs-wf_vblank-interruptible, DMESG_WARN(1, M26)PASS(3, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_flip_plain-flip, PASS(4, M26) -> DMESG_WARN(2, M26)PASS(2, M26)
ILK: Intel_gpu_tools, igt_kms_flip_vblank-vs-hang-interruptible, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_pipe_crc_basic_bad-nb-words-1, PASS(4, M26) -> DMESG_WARN(1, M26)PASS(3, M26)
ILK: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, FAIL(2, M26)DMESG_FAIL(1, M26)TIMEOUT(12, M37M6)PASS(1, M26) -> TIMEOUT(1, M26)PASS(3, M26)
IVB: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(4, M21M34)PASS(6, M34M21) -> NSPT(1, M34)PASS(3, M34)
IVB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(9, M34M21)PASS(1, M21) -> TIMEOUT(1, M34)PASS(3, M34)
SNB: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(17, M35M22)PASS(1, M35) -> TIMEOUT(1, M35)PASS(3, M35)
HSW: Intel_gpu_tools, igt_kms_flip_blocking-absolute-wf_vblank, PASS(4, M39) -> DMESG_WARN(1, M39)PASS(3, M39)
HSW: Intel_gpu_tools, igt_kms_setmode_clone-single-crtc, PASS(4, M39) -> DMESG_WARN(1, M39)PASS(3, M39)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, DMESG_WARN(1, M28)PASS(12, M42M30M28) -> PASS(4, M28)
BDW: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(10, M42M30M28)PASS(1, M28) -> TIMEOUT(1, M28)PASS(3, M28)
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit
2014-11-12 15:48 ` Daniel Vetter
@ 2014-11-13 7:19 ` Jani Nikula
2014-11-13 20:29 ` Daniel Vetter
0 siblings, 1 reply; 7+ messages in thread
From: Jani Nikula @ 2014-11-13 7:19 UTC (permalink / raw)
To: Daniel Vetter; +Cc: intel-gfx, shuang.he
On Wed, 12 Nov 2014, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Wed, Nov 12, 2014 at 05:01:10PM +0200, Jani Nikula wrote:
>> Use the same conditions, group by features, add comments.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_suspend.c | 18 +++++++++---------
>> 1 file changed, 9 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
>> index 3c1fccfacac1..dfe661743398 100644
>> --- a/drivers/gpu/drm/i915/i915_suspend.c
>> +++ b/drivers/gpu/drm/i915/i915_suspend.c
>> @@ -203,21 +203,19 @@ static void i915_save_display(struct drm_device *dev)
>> i915_save_display_reg(dev);
>>
>> /* LVDS state */
>> - if (HAS_PCH_SPLIT(dev)) {
>> - dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
>> - if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>> - dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
>> - } else if (!IS_VALLEYVIEW(dev)) {
>> - dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>> - if (IS_MOBILE(dev) && !IS_I830(dev))
>> - dev_priv->regfile.saveLVDS = I915_READ(LVDS);
>> - }
>> + if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>> + dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
>> + else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
>> + dev_priv->regfile.saveLVDS = I915_READ(LVDS);
>>
>> + /* Panel power sequencer */
>> if (HAS_PCH_SPLIT(dev)) {
>> + dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
>> dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
>> dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
>> dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
>> } else if (!IS_VALLEYVIEW(dev)) {
>> + dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
>> dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
>> dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
>> dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
>
> Just because they're in the context: Do we still need to restore the PP
> stuff with all the recent pps patches? Would be great to remove this ...
AFAICT we only do the full setup for vlv/chv at eDP mode set, and that's
because the pipe might have changed. Something similar might cut it for
lvds and non-vlv/chv eDP, but I'm not prepared to touch that just yet
after Ville's changes. I'd rather the dust settled a bit first. ;)
The lvds setup similarly seems to carry over bits all the way from boot
over suspend/resume cycles.
BR,
Jani.
>
> Anyway looks all good (and nicely frigthening ;-) so pulled all into dinq.
> -Daniel
>
>> @@ -246,11 +244,13 @@ static void i915_restore_display(struct drm_device *dev)
>> if (drm_core_check_feature(dev, DRIVER_MODESET))
>> mask = ~LVDS_PORT_EN;
>>
>> + /* LVDS state */
>> if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
>> I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
>> else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
>> I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
>>
>> + /* Panel power sequencer */
>> if (HAS_PCH_SPLIT(dev)) {
>> I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
>> I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
>> --
>> 2.1.1
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit
2014-11-13 7:19 ` Jani Nikula
@ 2014-11-13 20:29 ` Daniel Vetter
0 siblings, 0 replies; 7+ messages in thread
From: Daniel Vetter @ 2014-11-13 20:29 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, Patch Regression Testing System
On Thu, Nov 13, 2014 at 8:19 AM, Jani Nikula <jani.nikula@intel.com> wrote:
> The lvds setup similarly seems to carry over bits all the way from boot
> over suspend/resume cycles.
Yeah lvds setup definitely carries over bits through this means (the
lane setup specifically) which we don't restore in any other way.
That's why I didn't mention it.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2014-11-13 20:29 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-11-12 14:25 [PATCH 1/2] drm/i915: don't save/restore panel fitter registers Jani Nikula
2014-11-12 14:25 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist ctl registers Jani Nikula
2014-11-12 15:01 ` [PATCH 3/2] drm/i915: unify remaining register save/restore code a bit Jani Nikula
2014-11-12 15:48 ` Daniel Vetter
2014-11-13 7:19 ` Jani Nikula
2014-11-13 20:29 ` Daniel Vetter
2014-11-13 0:56 ` [PATCH 2/2] drm/i915: don't save/restore backlight hist shuang.he
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