From mboxrd@z Thu Jan 1 00:00:00 1970 From: shuang.he@intel.com Subject: Re: [PATCH 2/2] drm/i915: sanitize RPS resetting during GPU Date: 22 Nov 2014 15:17:10 -0800 Message-ID: <84c8a8$i837mg@orsmga001.jf.intel.com> References: <1416517308-12934-2-git-send-email-imre.deak@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 688966FBED for ; Sat, 22 Nov 2014 15:17:11 -0800 (PST) In-Reply-To: <1416517308-12934-2-git-send-email-imre.deak@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: shuang.he@intel.com, intel-gfx@lists.freedesktop.org, imre.deak@intel.com List-Id: intel-gfx@lists.freedesktop.org VGVzdGVkLUJ5OiBQUkMgUUEgUFJUUyAoUGF0Y2ggUmVncmVzc2lvbiBUZXN0IFN5c3RlbSBDb250 YWN0OiBzaHVhbmcuaGVAaW50ZWwuY29tKQotLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tU3VtbWFyeS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KUGxhdGZv cm0gICAgICAgICAgRGVsdGEgICAgICAgICAgZHJtLWludGVsLW5pZ2h0bHkgICAgICAgICAgU2Vy aWVzIEFwcGxpZWQKUE5WICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDM2Ny8zNjcg ICAgICAgICAgICAgIDM2Ny8zNjcKSUxLICAgICAgICAgICAgICAgICAtNCAgICAgICAgICAgICAg MzczLzM3NSAgICAgICAgICAgICAgMzY5LzM3NQpTTkIgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgNDUwLzQ1MCAgICAgICAgICAgICAgNDUwLzQ1MApJVkIgICAgICAgICAgICAgICAg IC0xICAgICAgICAgICAgICA1MDIvNTAzICAgICAgICAgICAgICA1MDEvNTAzCkJZVCAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAyODkvMjg5ICAgICAgICAgICAgICAyODkvMjg5CkhT VyAgICAgICAgICAgICAgICAgLTMgICAgICAgICAgICAgIDU2Ny81NjcgICAgICAgICAgICAgIDU2 NC81NjcKQkRXICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDQxNy80MTcgICAgICAg ICAgICAgIDQxNy80MTcKLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLURldGFp bGVkLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQpQbGF0Zm9ybSAgVGVzdCAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgZHJtLWludGVsLW5pZ2h0bHkgICAgICAgICAg U2VyaWVzIEFwcGxpZWQKSUxLICBpZ3Rfa21zX2ZsaXBfYmNzLWZsaXAtdnMtbW9kZXNldC1pbnRl cnJ1cHRpYmxlICAgICAgUEFTUygyLCBNMzdNMjYpICAgICAgRE1FU0dfV0FSTigxLCBNMjYpCklM SyAgaWd0X2ttc19mbGlwX2ZsaXAtdnMtZHBtcy1pbnRlcnJ1cHRpYmxlICAgICAgUEFTUygyLCBN MzdNMjYpICAgICAgRE1FU0dfV0FSTigxLCBNMjYpCklMSyAgaWd0X2ttc19mbGlwX2ZsaXAtdnMt cm1mYi1pbnRlcnJ1cHRpYmxlICAgICAgUEFTUygyLCBNMzdNMjYpICAgICAgRE1FU0dfV0FSTigx LCBNMjYpCklMSyAgaWd0X2ttc19mbGlwX3Jjcy1mbGlwLXZzLW1vZGVzZXQgICAgICBETUVTR19X QVJOKDEsIE0yNilQQVNTKDEsIE0zNykgICAgICBETUVTR19XQVJOKDEsIE0yNikKSVZCICBpZ3Rf Z2VtX2JhZF9yZWxvY19uZWdhdGl2ZS1yZWxvYy1sdXQgICAgICBOU1BUKDMsIE0yMU0zNE00KVBB U1MoMSwgTTIxKSAgICAgIE5TUFQoMiwgTTQpCkhTVyAgaWd0X2dlbV9iYWRfcmVsb2NfbmVnYXRp dmUtcmVsb2MtbHV0ICAgICAgTlNQVCg5LCBNNDBNMjApUEFTUygxLCBNMjApICAgICAgTlNQVCgx LCBNNDApCkhTVyAgaWd0X2ttc19yb3RhdGlvbl9jcmNfcHJpbWFyeS1yb3RhdGlvbiAgICAgIFBB U1MoMTAsIE0yME00MCkgICAgICBETUVTR19XQVJOKDEsIE00MCkKSFNXICBpZ3RfcG1fcmM2X3Jl c2lkZW5jeV9yYzYtYWNjdXJhY3kgICAgICBQQVNTKDEwLCBNMjBNNDApICAgICAgRkFJTCgxLCBN NDApCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVs LWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwOi8v bGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg==