From mboxrd@z Thu Jan 1 00:00:00 1970 From: shuang.he@intel.com Subject: Re: [PATCH 4/4] drm/i915: Use intel_gpu_freq() and intel_freq_opcode() Date: 27 Jan 2015 16:39:03 -0800 Message-ID: <84c8a8$j5o8uc@orsmga001.jf.intel.com> References: <1422039866-11572-5-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 54A726E366 for ; Tue, 27 Jan 2015 16:39:05 -0800 (PST) In-Reply-To: <1422039866-11572-5-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: shuang.he@intel.com, ethan.gao@intel.com, intel-gfx@lists.freedesktop.org, ville.syrjala@linux.intel.com List-Id: intel-gfx@lists.freedesktop.org VGVzdGVkLUJ5OiBQUkMgUUEgUFJUUyAoUGF0Y2ggUmVncmVzc2lvbiBUZXN0IFN5c3RlbSBDb250 YWN0OiBzaHVhbmcuaGVAaW50ZWwuY29tKQpUYXNrIGlkOiA1NjQxCi0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS1TdW1tYXJ5LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLQpQbGF0Zm9ybSAgICAgICAgICBEZWx0YSAgICAgICAgICBkcm0taW50ZWwtbmlnaHRs eSAgICAgICAgICBTZXJpZXMgQXBwbGllZApQTlYgICAgICAgICAgICAgICAgIC0xICAgICAgICAg ICAgICAzNTMvMzUzICAgICAgICAgICAgICAzNTIvMzUzCklMSyAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAzNTMvMzUzICAgICAgICAgICAgICAzNTMvMzUzClNOQiAgICAgICAgICAg ICAgKzEtMSAgICAgICAgICAgICAgNDAwLzQyMiAgICAgICAgICAgICAgNDAwLzQyMgpJVkIgICAg ICAgICAgICAgICsyLTEgICAgICAgICAgICAgIDQ4NS80ODcgICAgICAgICAgICAgIDQ4Ni80ODcK QllUICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIDI5Ni8yOTYgICAgICAgICAgICAg IDI5Ni8yOTYKSFNXICAgICAgICAgICAgICArMS0xICAgICAgICAgICAgICA1MDcvNTA4ICAgICAg ICAgICAgICA1MDcvNTA4CkJEVyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICA0MDEv NDAyICAgICAgICAgICAgICA0MDEvNDAyCi0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS1EZXRhaWxlZC0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0KUGxhdGZv cm0gIFRlc3QgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIGRybS1pbnRlbC1uaWdodGx5 ICAgICAgICAgIFNlcmllcyBBcHBsaWVkCipQTlYgIGlndF9nZW4zX3JlbmRlcl9saW5lYXJfYmxp dHMgICAgICBQQVNTKDMsIE0yNU0yMykgICAgICBDUkFTSCgxLCBNMjMpCipTTkIgIGlndF9rbXNf ZmxpcF9ldmVudF9sZWFrICAgICAgTlNQVCgzLCBNMzVNMjIpICAgICAgUEFTUygxLCBNMjIpCipT TkIgIGlndF9rbXNfZmxpcF90aWxpbmdfZmxpcC1jaGFuZ2VzLXRpbGluZyAgICAgIFBBU1MoMiwg TTM1TTIyKSAgICAgIEZBSUwoMSwgTTIyKQogSVZCICBpZ3RfZ2VtX3B3cml0ZV9wcmVhZF9zbm9v cGVkLXB3cml0ZS1ibHQtY3B1X21tYXAtcGVyZm9ybWFuY2UgICAgICBETUVTR19XQVJOKDIsIE0z NClQQVNTKDMsIE00KSAgICAgIFBBU1MoMSwgTTQpCiBJVkIgIGlndF9nZW1fc3RvcmVkd19iYXRj aGVzX2xvb3Bfbm9ybWFsICAgICAgRE1FU0dfV0FSTigyLCBNMzRNNClQQVNTKDUsIE0zNE00TTIx KSAgICAgIFBBU1MoMSwgTTQpCipJVkIgIGlndF9nZW1fc3RvcmVkd19iYXRjaGVzX2xvb3Bfc2Vj dXJlLWRpc3BhdGNoICAgICAgUEFTUygyLCBNMzRNNCkgICAgICBETUVTR19XQVJOKDEsIE00KQog SFNXICBpZ3RfZ2VtX3B3cml0ZV9wcmVhZF9zbm9vcGVkLXB3cml0ZS1ibHQtY3B1X21tYXAtcGVy Zm9ybWFuY2UgICAgICBETUVTR19XQVJOKDEsIE00MClQQVNTKDUsIE00ME0yMCkgICAgICBQQVNT KDEsIE0yMCkKIEhTVyAgaWd0X2dlbV9zdG9yZWR3X2xvb3BfdmVib3ggICAgICBETUVTR19XQVJO KDEsIE0yMClQQVNTKDIsIE00ME0yMCkgICAgICBETUVTR19XQVJOKDEsIE0yMCkKTm90ZTogWW91 IG5lZWQgdG8gcGF5IG1vcmUgYXR0ZW50aW9uIHRvIGxpbmUgc3RhcnQgd2l0aCAnKicKX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4IG1haWxp bmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0cy5mcmVl ZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK