From: shuang.he@intel.com
To: shuang.he@intel.com, ethan.gao@intel.com,
intel-gfx@lists.freedesktop.org, benjamin.widawsky@intel.com
Subject: Re: [PATCH 2/2] drm/i915: Add the last written reg to error state
Date: 20 Feb 2015 05:29:30 -0800 [thread overview]
Message-ID: <84c8a8$jgfb2a@orsmga001.jf.intel.com> (raw)
In-Reply-To: <1424410412-24910-2-git-send-email-benjamin.widawsky@intel.com>
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5799
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -2 277/277 275/277
ILK 313/313 313/313
SNB -1 309/309 308/309
IVB 382/382 382/382
BYT 296/296 296/296
HSW -1 425/425 424/425
BDW -1 318/318 317/318
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_gem_userptr_blits_coherency-sync NO_RESULT(1)CRASH(5)NRUN(1)PASS(6) CRASH(2)
PNV igt_gem_userptr_blits_coherency-unsync CRASH(3)NRUN(1)PASS(4) CRASH(2)
*SNB igt_kms_plane_plane-panning-top-left-pipe-B-plane-2 PASS(2) TIMEOUT(1)PASS(1)
*HSW igt_gem_storedw_batches_loop_secure-dispatch PASS(2) DMESG_WARN(1)PASS(1)
*BDW igt_gem_gtt_hog PASS(17) DMESG_WARN(1)PASS(1)
Note: You need to pay more attention to line start with '*'
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next prev parent reply other threads:[~2015-02-20 13:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-20 5:33 [PATCH 1/2] drm/i915: Track last register written (debug) Ben Widawsky
2015-02-20 5:33 ` [PATCH 2/2] drm/i915: Add the last written reg to error state Ben Widawsky
2015-02-20 12:04 ` Chris Wilson
2015-02-20 13:29 ` shuang.he [this message]
2015-02-20 11:55 ` [PATCH 1/2] drm/i915: Track last register written (debug) Paulo Zanoni
2015-02-20 11:58 ` Chris Wilson
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