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[87.205.5.123]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65949ed6b7esm1664299a12.11.2026.02.04.15.06.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Feb 2026 15:06:16 -0800 (PST) Message-ID: <85ae9f0a13e33eae0be857753c4dc9037e9fa91b.camel@gmail.com> Subject: Re: [Intel-gfx] [RFC 00/15] Add support for HDMI2.1 FRL From: Tomasz =?UTF-8?Q?Paku=C5=82a?= To: Ankit Nautiyal , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Date: Thu, 05 Feb 2026 00:06:15 +0100 In-Reply-To: <20221107072045.628895-1-ankit.k.nautiyal@intel.com> References: <20221107072045.628895-1-ankit.k.nautiyal@intel.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.2 MIME-Version: 1.0 X-Mailman-Approved-At: Thu, 05 Feb 2026 14:08:00 +0000 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 2022-11-07 at 12:50 +0530, Ankit Nautiyal wrote: > This set is RFC for adding support for HDMI2.1 FRL Link training. > FRL or Fixed Rate Link is defined by HDMI2.1 spec for supporting higher > bit-rate. As per HDMI2.1 specification, a new data-channel or lane is > added in FRL mode, by repurposing the TMDS clock Channel. This enables > HDMI to support 48 Gbps bandwidth (i.e. bit rate of 12 Gbps/lane for 4 > lanes). >=20 > This series is a step for Native HDMI2.1 support for MTL and to begin > discussion on the Fixed Rate Link Training part. It adds new structures, > registers and functions for facilitating FRL training for HDMI2.1. > Basically it provides the support for starting the Link training for a > given bit rate and lane count. >=20 > The appropriate bit rate and lanes need to be computed in the compute > config phase for HDMI, for a given video-mode, which is not part of this > series, but can be built on the basic structures and new members added > in this series. The FRL Training will take place only when we take a > decision to go for FRL mode and set the crtc_state parameters > appropriately during compute config phase. >=20 > The first 2 patches are prep work to have helper for getting MAX > FRL rate for existing DP-to HDMI2.1 PCON and Native HDMI2.1 from an > older series: https://patchwork.freedesktop.org/series/99311/ >=20 > As HDMI2.1 needs C20 PHY, there is dependency on patch series from > Mika: https://patchwork.freedesktop.org/series/109714/ > Therefore Patch 3 which adds the C10/C20 registers, is taken from the > above series for completeness, and FRL bits are added on top of that. >=20 > Ankit Nautiyal (13): > drm/edid: Add helper to get max FRL rate for an HDMI sink > drm/i915/dp: Use the drm helpers for getting max FRL rate > drm/i915/hdmi21/mtl: Add new data members for FRL configuration > drm/drm_scdc_helper: Add SCDC helper funcs for HDMI2.1 > drm/i915/mtl: Add registers for FRL Link Training > drm/i915/mtl: Add HDMI2.1 bits in PORT_BUF_CTL_1 > drm/i915/mtl: Add port_data/data width for TRANS_DDI_FUNC and > DDI_BUF_CTL > drm/i915/display/mtl: Add new members in crtc_state for FRL > configuration > drm/i915/display/mtl: Update Transcoder/DDI registers with the frl > bits > drm/i915/display/mtl: Reset FRL Transcoder config while disabling HDMI > drm/i915/hdmi21/mtl: Enable Scrambling only for FRL mode > drm/i915/hdmi21/mtl: Add support for sending uevent to user for FRL > training failure > drm/i915/display/mtl: Add functions for FRL trainining state machine >=20 > Mika Kahola (1): > drm/i915/mtl: Create separate reg file for PICA registers >=20 > Vandita Kulkarni (1): > drm/i915/hdmi21/mtl: Parse frl max link rate from vbt >=20 > drivers/gpu/drm/display/drm_scdc_helper.c | 196 ++++++++ > drivers/gpu/drm/drm_edid.c | 38 ++ > drivers/gpu/drm/i915/display/intel_bios.c | 51 ++ > drivers/gpu/drm/i915/display/intel_bios.h | 1 + > .../gpu/drm/i915/display/intel_cx0_reg_defs.h | 144 ++++++ > drivers/gpu/drm/i915/display/intel_ddi.c | 63 ++- > .../drm/i915/display/intel_display_types.h | 32 ++ > drivers/gpu/drm/i915/display/intel_dp.c | 17 +- > drivers/gpu/drm/i915/display/intel_hdmi.c | 443 +++++++++++++++++- > drivers/gpu/drm/i915/display/intel_hdmi.h | 2 + > drivers/gpu/drm/i915/display/intel_vbt_defs.h | 7 + > drivers/gpu/drm/i915/i915_reg.h | 33 +- > include/drm/display/drm_scdc.h | 23 + > include/drm/display/drm_scdc_helper.h | 21 + > include/drm/drm_edid.h | 2 + > 15 files changed, 1052 insertions(+), 21 deletions(-) > create mode 100644 drivers/gpu/drm/i915/display/intel_cx0_reg_defs.h Does anybody know why this wasn't pursued further? I can't find anything about FRL support in i915 as far as 6.18. Is it HDMI forum again? Is there even anything left to hide at this point?