From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: [PATCH 09/12] Do more checks for proposed flip pixmaps Date: Wed, 30 Jul 2014 23:01:48 -0700 Message-ID: <864mxydq2b.fsf@hiro.keithp.com> References: <1406243908-1123-1-git-send-email-keithp@keithp.com> <1406243908-1123-10-git-send-email-keithp@keithp.com> <87a97qe1ia.fsf@eliezer.anholt.net> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0084481756==" Return-path: In-Reply-To: <87a97qe1ia.fsf@eliezer.anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Eric Anholt , xorg-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org --===============0084481756== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --=-=-= Content-Type: text/plain Content-Transfer-Encoding: quoted-printable Eric Anholt writes: > Keith Packard writes: > >> Make sure the pitch and tiling are correct. >> Make sure there's a BO we can get at. > > I thought we couldn't change these parameters, but now I can't find what > prevents them from changing. Can you cite sources? Looks like we *can* change tiling format. That actually makes me kinda happy as that explains why we were able to allocate a linear frame buffer for the X front buffer (due to a bug) and page flip to DRI3 buffers which are always tiled. However, we can't change the pitch. From the kernel driver: /* * TILEOFF/LINOFF registers can't be changed via MI display flips. * Note that pitch changes could also affect these register. */ if (INTEL_INFO(dev)->gen > 3 && (fb->offsets[0] !=3D crtc->primary->fb->offsets[0] || fb->pitches[0] !=3D crtc->primary->fb->pitches[0])) return -EINVAL; I'll remove the tiling check. =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIVAwUBU9nbzNsiGmkAAAARAQhfYQ//aFnZucXU0PLj1tO013Q30kWAM3QkCipf xQ7qeiehvl0F+JQcjf1Kxe6CtxTRlmmfK9MMq8XIarJUORK/yLHKu5Fztpi+V+yF 7+j25V5Qby7sLjfYA1HOTgm8FcvtN4s8D6IQBYqjWPFbtwWRLCsCVkhvb2w9jsBN rVVtqRsAWkUm11iRDOV3ICOBOjwHEjxGDF0TMK5ffYh8MDy10S8vpvIxtrJ7D1+R A0OBr+5pWOIxpgCn4IGxGgZ5bthhdyJjZuiBW8y9F16x3UcEjtpbY3re21MDutlA fXEH9XUudRvGK/K/kkT+kQDSG/brhrdMIol0e/fyrlY2ItARhSwBrng0GGGNUYnQ NWK87UR5PR1Y+GLnNGaR8SXq5QL1KX30F3Rv0BD/JAEHw6ph53EloUKL2oaGa/Ub fwlXI1BTqPsQbJAFc6qZuDu540/o4YrncRgkz2j9YQT5X2lDtJf3k0P117bIY+FY XLZ0nX1D5T9sh8nKza6n3VmQsOIs6rTzU0PospLpMSCuiBKWvU69HpwhKTiH4anj 9Fqi3dX2a9Xu2q1ENDiODByfN0YFdz/+x02+sMgw3oD52j7DI9kUXaH+I+LT1gei t5d7oD8tpEZ0bpQw0WGr/iD5+e7Cl3Dixf+fPArCJ1KY7WJ4Efnq4Ho23OXNiAjE RDSdWMCoRxo= =t9oC -----END PGP SIGNATURE----- --=-=-=-- --===============0084481756== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0084481756==--