From: Keith Packard <keithp-aN4HjG94KOLQT0dZR+AlfA@public.gmane.org>
To: Chris Wilson <chris-Y6uKTt2uX1cEflXRtASbqLVCufUGDwFn@public.gmane.org>
Cc: xorg-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
intel-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Subject: Re: [Intel-gfx] [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA
Date: Sat, 13 Sep 2014 10:31:28 -0700 [thread overview]
Message-ID: <86ha0bs9zj.fsf@hiro.keithp.com> (raw)
In-Reply-To: <20140913082824.GM16043-aII6DKEyn0pWYbfKqPwjAkR8Iwp7RQ6xAL8bYrjMMd8@public.gmane.org>
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Chris Wilson <chris-Y6uKTt2uX1cEflXRtASbqLVCufUGDwFn@public.gmane.org> writes:
> commit d21d781466785c317131a8a57606925867265dc8
> Author: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
> Date: Tue Feb 22 18:31:44 2011 +0100
>
> Fix relaxed tiling on gen2
This one matches libdrm in using 16 for the tile height alignment on
gen2.
> Try enabling relaxed fencing again.
> No. The clearest requirement is that the ddx (or other display server)
> must treat incoming surfaces as tainted and validate them to be sure
> that they work with its code paths. If it can't we have a choice of
> either rejecting them outright, or staging them.
If there's a stricter alignment requirement, then we must fix both the
2D driver and libdrm. Otherwise, the user's session will simply crash at
startup.
However, I still see absolutely no evidence that gen2 requires tile
alignment to 32 rows, or that gen3+ requires tile alignment to 16
rows in any software configuration at all.
--
keith.packard-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org
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xorg-devel-go0+a7rfsptAfugRpC6u6w@public.gmane.org: X.Org development
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next prev parent reply other threads:[~2014-09-13 17:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-10 21:09 [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA Keith Packard
[not found] ` <1410383349-27678-1-git-send-email-keithp-aN4HjG94KOLQT0dZR+AlfA@public.gmane.org>
2014-09-10 21:09 ` [PATCH 1/2] Do not clear pending kernel events on mode switch Keith Packard
2014-09-10 21:09 ` [PATCH 2/2] Correct BO allocation alignment Keith Packard
2014-09-11 6:37 ` [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA Chris Wilson
[not found] ` <20140911063716.GB28332-aII6DKEyn0pWYbfKqPwjAkR8Iwp7RQ6xAL8bYrjMMd8@public.gmane.org>
2014-09-11 6:47 ` [Intel-gfx] " Jasper St. Pierre
2014-09-11 6:52 ` Chris Wilson
2014-09-11 19:53 ` [Intel-gfx] " Keith Packard
[not found] ` <86r3ziorwl.fsf-6d7jPg3SX/+z9DMzp4kqnw@public.gmane.org>
2014-09-13 8:28 ` Chris Wilson
[not found] ` <20140913082824.GM16043-aII6DKEyn0pWYbfKqPwjAkR8Iwp7RQ6xAL8bYrjMMd8@public.gmane.org>
2014-09-13 17:31 ` Keith Packard [this message]
2014-09-12 19:13 ` Kenneth Graunke
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