Re: [Intel-gfx] [PATCH 0/2 xf86-video-intel] Two DRI3/Present bug fixes for UXA

Jasper St. Pierre
2014-09-11T06:47:21Z

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Why doesn't mesa allocate buffers in the same way for those chips, then?

Do you have any documentation about this?

On Thu, Sep 11, 2014 at 12:37 AM, Chris Wilson <chris-Y6uKTt2uX1cEflXRtASbqLVCufUGDwFn@public.gmane.org>
wrote:

> On Wed, Sep 10, 2014 at 02:09:07PM -0700, Keith Packard wrote:
> > [PATCH 2/2] Correct BO allocation alignment
> >
> > This patch makes UXA and Mesa agree about how buffers are allocated
> > for images. Without this, UXA was requiring larger padding, which
> > meant that converting some textures into pixmaps using DRI3 would
> > fail.
>
> That extra alignment is due to gen2 and early gen3 (if
> (!intel->has_relaxed_fencing) covers them).
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
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--
Jasper

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