From mboxrd@z Thu Jan 1 00:00:00 1970 From: Keith Packard Subject: Re: [PATCH 06/43] drm/i915: protect force_wake_(get|put) with the gt_lock Date: Thu, 05 Jan 2012 16:29:43 -0800 Message-ID: <86k4558yh4.fsf@sumi.keithp.com> References: <86wr98mqw3.fsf@sumi.keithp.com> <86obukmkdq.fsf@sumi.keithp.com> <86zke3l5fj.fsf@sumi.keithp.com> <20120104181257.GI8004@phenom.ffwll.local> <86fwfulwge.fsf@sumi.keithp.com> <20120105112908.GB3831@phenom.ffwll.local> <86y5tm8807.fsf@sumi.keithp.com> <20120105165947.GG3831@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0464649513==" Return-path: Received: from keithp.com (home.keithp.com [63.227.221.253]) by gabe.freedesktop.org (Postfix) with ESMTP id 425189E81C for ; Thu, 5 Jan 2012 16:29:49 -0800 (PST) In-Reply-To: <20120105165947.GG3831@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Daniel Vetter , intel-gfx List-Id: intel-gfx@lists.freedesktop.org --===============0464649513== Content-Type: multipart/signed; boundary="=-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --=-=-= Content-Transfer-Encoding: quoted-printable On Thu, 5 Jan 2012 17:59:47 +0100, Daniel Vetter wrote: > Absolutely agreed, maybe with the adadendum to only try to make things > faster if it's actually a problem and shows up in a fast-path we care > about. Here's a longer series that does a bunch of cleanup before trying to fix things. Patches marked with '***' fix bugs. The patch marked with '...' is the optimization to inline the spinlocks. The following changes since commit d8e70a254d8f2da141006e496a51502b79115e80: drm/i915: only set the intel_crtc DPMS mode to on if the mode set succeed= ed (2012-01-03 14:55:52 -0800) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux forcewake-spin= lock Keith Packard (9): drm/i915: Split register access functions out from display functions The forcewake functions are invoked unconditionally on >=3D gen6 hardware from the register read/write functions. Having these initialized as a side-effect of display initialization seems wrong to me. I've moved the functions out of the display structure and into a separate structure, and moved the initialization to driver load time. drm/i915: Access registers through function pointers This makes register access go through function pointers, following similar changes in many other parts of the driver. drm/i915: Split out reg read/write for pre/post gen6 hardware Taking advantage of the previous indirection, this actually creates separate register read/write functions for pre-gen6 and post-gen6 hardware. drm/i915: Move forcewake_count to reg_access structure Just moves the count into the new structure to keep things together. drm/i915: hide forcewake_count behind i915_forcewake_count Create a function to hide getting the forcewake_count value drm/i915: Switch forcewake from atomic to using a spinlock This changes the type from atomic to u32 and wraps all users in a new spinlock. The spinlock is held across calls to ->force_wake_put and ->force_wake_get. *** drm/i915: Hold forcewake spinlock across reset process Changes the reset process to hold the spinlock -- this will ensure that all register operations will be correct wrt the spinlock, even if the hardware gets reset. *** drm/i915: Hold forcewake spinlock during register write operations This protects the gt_fifo_count value under the spinlock and keeps modifications to that tied to the actual register write. ... drm/i915: inline spin_lock usage in register read macros Here's the optimization I mentioned -- inlines the spinlocks inside the register read operations. =2D-=20 keith.packard@intel.com --=-=-= Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIVAwUBTwZAdzYtFsjWk68qAQh2cA//VNUtHuFKgX6/pCnE7973xzQtcoi0nCT6 /RJC5qBiwFrBkXqI+Qre7WwLQg66paul3CJtEQAdXZL1vYPVyc9zjehrkJ5MawmS mHfsajzng8/joEW7GVBA3TxbUMFs8OKcaTUVwnji9ATvx72XkGsjhLt6NZrUOEfT dt52UkQeqzrjOyHMmpHD6akcAUB4dmFZR86X9IXkAbU3aMyEFMl7ROIpQQhptrND sTk+ypw4DDPhU49PYt1PVJjOZIxQ2dM5yB11tQDGqjuYxSwYFGjy2N39UvUa/vNi qZCkGRAHaA7yMBzlL4/AKrK7S8QZ09LoqUkUOtvjhOVAjzAcEdUsnrr0JWrOAAlP VcOmRlXr86U3hXL10PI4Td1xJ1nm4qOGsHLYHEkx9rahF8J7ZUAxjIvtyzITqAIz e90SmFreDx7vqsv/NLXCmTS36vpELZqnvt3sebkuQeAXUqoV5730TDFMwYsghB/2 jpfrQZ9gK4JeV55/CPqOpmsyZrklWGow3zzxpdDExjwXhBI2WXC705HTZRJ7Em+P +L/CgDhfStRQDclwUN/2AmwZBrBEQ5GOZax6I1tUGHplPj21WxNZJYb0inyx3ZfX 6Ao7qBOx1MY0ANC6Hgm+QDxIzJoojBb+i5mRPJU+MVbP7XddVqhkfOC9Up28Askv IrvMEQmSaRk= =9snv -----END PGP SIGNATURE----- --=-=-=-- --===============0464649513== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx --===============0464649513==--