* [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds
@ 2017-09-27 9:33 Chris Wilson
2017-09-27 9:33 ` [PATCH 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Chris Wilson @ 2017-09-27 9:33 UTC (permalink / raw)
To: intel-gfx
We've begun excluding pre-production Broxton machines since commit
0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of preproduction
machines"), now remove the list of workaround register values for those
early machines.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 56 +---------------------------------
1 file changed, 1 insertion(+), 55 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index a28e2a864cf1..cd51d81ec6f4 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -994,22 +994,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
- /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
- GEN9_DG_MIRROR_FIX_ENABLE);
-
- /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
- GEN9_RHWO_OPTIMIZATION_DISABLE);
- /*
- * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
- * but we do that in per ctx batchbuffer as there is an issue
- * with this register not getting restored on ctx restore
- */
- }
-
/* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
/* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
@@ -1025,11 +1009,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
GEN9_CCS_TLB_PREFETCH_ENABLE);
- /* WaDisableMaskBasedCammingInRCC:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
- PIXEL_MASK_CAMMING_DISABLE);
-
/* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
WA_SET_BIT_MASKED(HDC_CHICKEN0,
HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
@@ -1059,8 +1038,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
/* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
if (IS_SKYLAKE(dev_priv) ||
IS_KABYLAKE(dev_priv) ||
- IS_COFFEELAKE(dev_priv) ||
- IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
+ IS_COFFEELAKE(dev_priv))
WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
GEN8_SAMPLER_POWER_BYPASS_DIS);
@@ -1178,17 +1156,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
if (ret)
return ret;
- /* WaStoreMultiplePTEenable:bxt */
- /* This is a requirement according to Hardware specification */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
- I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
-
- /* WaSetClckGatingDisableMedia:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
- ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
- }
-
/* WaDisableThreadStallDopClockGating:bxt */
WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
STALL_DOP_GATING_DISABLE);
@@ -1199,27 +1166,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
_MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
}
- /* WaDisableSbeCacheDispatchPortSharing:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
- WA_SET_BIT_MASKED(
- GEN7_HALF_SLICE_CHICKEN1,
- GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
- }
-
- /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
- /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
- /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
- /* WaDisableLSQCROPERFforOCL:bxt */
- if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
- ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
- if (ret)
- return ret;
-
- ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
- if (ret)
- return ret;
- }
-
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915: Unconditionally apply the Broxton register workaround set
2017-09-27 9:33 [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
@ 2017-09-27 9:33 ` Chris Wilson
2017-09-27 10:40 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Chris Wilson @ 2017-09-27 9:33 UTC (permalink / raw)
To: intel-gfx
Having removed the preproduction Broxton support (see commit 0102ba1fd8af
("drm/i915: Add early BXT sdv to the list of preproduction machines")),
we know we then always need the production Broxton workaround set and do
not need a predicate upon revision.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_engine_cs.c | 23 +++++++++--------------
1 file changed, 9 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index cd51d81ec6f4..6529f46a125a 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1161,26 +1161,21 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
STALL_DOP_GATING_DISABLE);
/* WaDisablePooledEuLoadBalancingFix:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) {
- I915_WRITE(FF_SLICE_CS_CHICKEN2,
- _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
- }
+ I915_WRITE(FF_SLICE_CS_CHICKEN2,
+ _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
/* WaProgramL3SqcReg1DefaultForPerf:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
- I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
- L3_HIGH_PRIO_CREDITS(2));
+ I915_WRITE(GEN8_L3SQCREG1,
+ L3_GENERAL_PRIO_CREDITS(62) | L3_HIGH_PRIO_CREDITS(2));
/* WaToEnableHwFixForPushConstHWBug:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
- WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
- GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
+ WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
+ GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
/* WaInPlaceDecompressionHang:bxt */
- if (IS_BXT_REVID(dev_priv, BXT_REVID_C0, REVID_FOREVER))
- I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
- (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
- GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
+ I915_WRITE(GEN9_GAMT_ECO_REG_RW_IA,
+ (I915_READ(GEN9_GAMT_ECO_REG_RW_IA) |
+ GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS));
return 0;
}
--
2.14.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-09-27 9:33 [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
2017-09-27 9:33 ` [PATCH 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
@ 2017-09-27 10:40 ` Patchwork
2017-09-27 14:10 ` [PATCH 1/2] " Jani Nikula
2017-09-27 14:14 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-09-27 10:40 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds
URL : https://patchwork.freedesktop.org/series/30952/
State : success
== Summary ==
Series 30952v1 series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds
https://patchwork.freedesktop.org/api/1.0/series/30952/revisions/1/mbox/
Test pm_rpm:
Subgroup basic-rte:
pass -> DMESG-WARN (fi-cfl-s) fdo#102294
Test drv_module_reload:
Subgroup basic-reload:
pass -> DMESG-WARN (fi-glk-1) fdo#102777 +2
fdo#102294 https://bugs.freedesktop.org/show_bug.cgi?id=102294
fdo#102777 https://bugs.freedesktop.org/show_bug.cgi?id=102777
fi-bdw-5557u total:289 pass:268 dwarn:0 dfail:0 fail:0 skip:21 time:443s
fi-bdw-gvtdvm total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:471s
fi-blb-e6850 total:289 pass:224 dwarn:1 dfail:0 fail:0 skip:64 time:417s
fi-bsw-n3050 total:289 pass:243 dwarn:0 dfail:0 fail:0 skip:46 time:505s
fi-bwr-2160 total:289 pass:184 dwarn:0 dfail:0 fail:0 skip:105 time:278s
fi-bxt-j4205 total:289 pass:260 dwarn:0 dfail:0 fail:0 skip:29 time:496s
fi-byt-j1900 total:289 pass:254 dwarn:1 dfail:0 fail:0 skip:34 time:492s
fi-cfl-s total:289 pass:222 dwarn:35 dfail:0 fail:0 skip:32 time:537s
fi-cnl-y total:289 pass:258 dwarn:0 dfail:0 fail:4 skip:27 time:653s
fi-elk-e7500 total:289 pass:230 dwarn:0 dfail:0 fail:0 skip:59 time:418s
fi-glk-1 total:289 pass:259 dwarn:1 dfail:0 fail:0 skip:29 time:566s
fi-hsw-4770 total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:430s
fi-hsw-4770r total:289 pass:263 dwarn:0 dfail:0 fail:0 skip:26 time:404s
fi-ilk-650 total:289 pass:229 dwarn:0 dfail:0 fail:0 skip:60 time:434s
fi-ivb-3520m total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:479s
fi-ivb-3770 total:289 pass:261 dwarn:0 dfail:0 fail:0 skip:28 time:464s
fi-kbl-7500u total:289 pass:264 dwarn:1 dfail:0 fail:0 skip:24 time:474s
fi-kbl-7560u total:289 pass:270 dwarn:0 dfail:0 fail:0 skip:19 time:584s
fi-kbl-r total:289 pass:262 dwarn:0 dfail:0 fail:0 skip:27 time:587s
fi-pnv-d510 total:289 pass:223 dwarn:1 dfail:0 fail:0 skip:65 time:544s
fi-skl-6260u total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:453s
fi-skl-6700k total:289 pass:265 dwarn:0 dfail:0 fail:0 skip:24 time:747s
fi-skl-6770hq total:289 pass:269 dwarn:0 dfail:0 fail:0 skip:20 time:489s
fi-skl-gvtdvm total:289 pass:266 dwarn:0 dfail:0 fail:0 skip:23 time:470s
fi-snb-2520m total:289 pass:251 dwarn:0 dfail:0 fail:0 skip:38 time:569s
fi-snb-2600 total:289 pass:250 dwarn:0 dfail:0 fail:0 skip:39 time:410s
da14aaa14e584a49e94bffd3c7af6e659745bae6 drm-tip: 2017y-09m-27d-09h-50m-55s UTC integration manifest
b601b536d772 drm/i915: Unconditionally apply the Broxton register workaround set
d9f810c4e720 drm/i915: Remove pre-production Broxton register workarounds
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5829/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-09-27 9:33 [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
2017-09-27 9:33 ` [PATCH 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
2017-09-27 10:40 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds Patchwork
@ 2017-09-27 14:10 ` Jani Nikula
2017-09-27 14:14 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
3 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2017-09-27 14:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On Wed, 27 Sep 2017, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> We've begun excluding pre-production Broxton machines since commit
> 0102ba1fd8af ("drm/i915: Add early BXT sdv to the list of preproduction
> machines"), now remove the list of workaround register values for those
> early machines.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
On the series,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Side note #1, should we throw out the old unused stepping macros?
Side note #2, we seem to be missing a bunch of platforms from
intel_detect_preproduction_hw(). At least KBL, GLK, CFL, and CNL would
be relevant. I suppose we could also remove HSW check in there, and
assume nobody would use a pre-production version of such an old thing?
> ---
> drivers/gpu/drm/i915/intel_engine_cs.c | 56 +---------------------------------
> 1 file changed, 1 insertion(+), 55 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a28e2a864cf1..cd51d81ec6f4 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -994,22 +994,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
>
> - /* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> - GEN9_DG_MIRROR_FIX_ENABLE);
> -
> - /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
> - GEN9_RHWO_OPTIMIZATION_DISABLE);
> - /*
> - * WA also requires GEN9_SLICE_COMMON_ECO_CHICKEN0[14:14] to be set
> - * but we do that in per ctx batchbuffer as there is an issue
> - * with this register not getting restored on ctx restore
> - */
> - }
> -
> /* WaEnableYV12BugFixInHalfSliceChicken7:skl,bxt,kbl,glk,cfl */
> /* WaEnableSamplerGPGPUPreemptionSupport:skl,bxt,kbl,cfl */
> WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
> @@ -1025,11 +1009,6 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
> GEN9_CCS_TLB_PREFETCH_ENABLE);
>
> - /* WaDisableMaskBasedCammingInRCC:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - WA_SET_BIT_MASKED(SLICE_ECO_CHICKEN0,
> - PIXEL_MASK_CAMMING_DISABLE);
> -
> /* WaForceContextSaveRestoreNonCoherent:skl,bxt,kbl,cfl */
> WA_SET_BIT_MASKED(HDC_CHICKEN0,
> HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> @@ -1059,8 +1038,7 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
> /* WaDisableSamplerPowerBypassForSOPingPong:skl,bxt,kbl,cfl */
> if (IS_SKYLAKE(dev_priv) ||
> IS_KABYLAKE(dev_priv) ||
> - IS_COFFEELAKE(dev_priv) ||
> - IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0))
> + IS_COFFEELAKE(dev_priv))
> WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
> GEN8_SAMPLER_POWER_BYPASS_DIS);
>
> @@ -1178,17 +1156,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> if (ret)
> return ret;
>
> - /* WaStoreMultiplePTEenable:bxt */
> - /* This is a requirement according to Hardware specification */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
> - I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
> -
> - /* WaSetClckGatingDisableMedia:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) &
> - ~GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE));
> - }
> -
> /* WaDisableThreadStallDopClockGating:bxt */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> STALL_DOP_GATING_DISABLE);
> @@ -1199,27 +1166,6 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> _MASKED_BIT_ENABLE(GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE));
> }
>
> - /* WaDisableSbeCacheDispatchPortSharing:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_B0)) {
> - WA_SET_BIT_MASKED(
> - GEN7_HALF_SLICE_CHICKEN1,
> - GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
> - }
> -
> - /* WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt */
> - /* WaDisableObjectLevelPreemptionForInstancedDraw:bxt */
> - /* WaDisableObjectLevelPreemtionForInstanceId:bxt */
> - /* WaDisableLSQCROPERFforOCL:bxt */
> - if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
> - ret = wa_ring_whitelist_reg(engine, GEN9_CS_DEBUG_MODE1);
> - if (ret)
> - return ret;
> -
> - ret = wa_ring_whitelist_reg(engine, GEN8_L3SQCREG4);
> - if (ret)
> - return ret;
> - }
> -
> /* WaProgramL3SqcReg1DefaultForPerf:bxt */
> if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
> I915_WRITE(GEN8_L3SQCREG1, L3_GENERAL_PRIO_CREDITS(62) |
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds
2017-09-27 9:33 [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
` (2 preceding siblings ...)
2017-09-27 14:10 ` [PATCH 1/2] " Jani Nikula
@ 2017-09-27 14:14 ` Patchwork
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2017-09-27 14:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds
URL : https://patchwork.freedesktop.org/series/30952/
State : success
== Summary ==
Test perf:
Subgroup polling:
pass -> FAIL (shard-hsw) fdo#102252
Test kms_flip:
Subgroup wf_vblank-vs-modeset:
pass -> DMESG-WARN (shard-hsw) fdo#102614
Test kms_setmode:
Subgroup basic:
fail -> PASS (shard-hsw) fdo#99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
fdo#102614 https://bugs.freedesktop.org/show_bug.cgi?id=102614
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
shard-hsw total:2429 pass:1335 dwarn:2 dfail:0 fail:9 skip:1083 time:9999s
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5829/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2017-09-27 14:14 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2017-09-27 9:33 [PATCH 1/2] drm/i915: Remove pre-production Broxton register workarounds Chris Wilson
2017-09-27 9:33 ` [PATCH 2/2] drm/i915: Unconditionally apply the Broxton register workaround set Chris Wilson
2017-09-27 10:40 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Remove pre-production Broxton register workarounds Patchwork
2017-09-27 14:10 ` [PATCH 1/2] " Jani Nikula
2017-09-27 14:14 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
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