From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [GLK MIPI DSI V1 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Date: Wed, 14 Dec 2016 13:46:44 +0200 Message-ID: <871sxaspgb.fsf@intel.com> References: <1481187003-15271-1-git-send-email-madhav.chauhan@intel.com> <1481187003-15271-2-git-send-email-madhav.chauhan@intel.com> <877f74t60i.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 61E3A6E7BD for ; Wed, 14 Dec 2016 11:46:52 +0000 (UTC) In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Chauhan, Madhav" , "intel-gfx@lists.freedesktop.org" Cc: "Conselvan De Oliveira, Ander" , "Deepak, M" , "Kumar, Shobhit" List-Id: intel-gfx@lists.freedesktop.org T24gV2VkLCAxNCBEZWMgMjAxNiwgIkNoYXVoYW4sIE1hZGhhdiIgPG1hZGhhdi5jaGF1aGFuQGlu dGVsLmNvbT4gd3JvdGU6Cj4gT3ZlcmFsbCwgYW55IGJpdCBmaWVsZC9yZWdpc3RlciAoYWRkZWQg aW4gdGhpcyBzZXJpZXMpIHNwZWNpZmljIHRvIEdMSwo+IHNob3VsZCBoYXZlIEdMS18gYW5kIGNv bW1vbiB0byBHTEsvQlhUIHNob3VsZCBoYXZlIEdFTjlMUF8gPz8KCkl0J3MgYSBsb25nIHN0YW5k aW5nIGNvbnZlbnRpb24gaW4gdGhlIGRyaXZlciB0byBuYW1lIHRoaW5ncyBhZnRlciB0aGUKZmly c3QgcGxhdGZvcm0gdGhleSB3ZXJlIGludHJvZHVjZWQgaW4uCgpCUiwKSmFuaS4KCgotLSAKSmFu aSBOaWt1bGEsIEludGVsIE9wZW4gU291cmNlIFRlY2hub2xvZ3kgQ2VudGVyCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxp c3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNr dG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo=