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From: Jani Nikula <jani.nikula@linux.intel.com>
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org
Cc: Deepak M <m.deepak@intel.com>
Subject: Re: [PATCH 04/16] drm/i915: Add a local pipe variable to	vlv_enable_pll()
Date: Wed, 16 Mar 2016 11:03:39 +0200	[thread overview]
Message-ID: <871t7ax09g.fsf@intel.com> (raw)
In-Reply-To: <1458052809-23426-5-git-send-email-ville.syrjala@linux.intel.com>

On Tue, 15 Mar 2016, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Avoid redundant crtc->pipe lookups by giving vlv_enable_pll() a local
> pipe variable. Also makes it look more like the corresponding CHV code.
>
> While at is change the CHV code to enum pipe from int,
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Jani Nikula <jani.nikula@intel.com>


> ---
>  drivers/gpu/drm/i915/intel_display.c | 17 +++++++++--------
>  1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 18158b0324ed..638ce97777de 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1572,24 +1572,25 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	i915_reg_t reg = DPLL(crtc->pipe);
> +	enum pipe pipe = crtc->pipe;
> +	i915_reg_t reg = DPLL(pipe);
>  	u32 dpll = pipe_config->dpll_hw_state.dpll;
>  
> -	assert_pipe_disabled(dev_priv, crtc->pipe);
> +	assert_pipe_disabled(dev_priv, pipe);
>  
>  	/* PLL is protected by panel, make sure we can write it */
>  	if (IS_MOBILE(dev_priv->dev))
> -		assert_panel_unlocked(dev_priv, crtc->pipe);
> +		assert_panel_unlocked(dev_priv, pipe);
>  
>  	I915_WRITE(reg, dpll);
>  	POSTING_READ(reg);
>  	udelay(150);
>  
>  	if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> -		DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
> +		DRM_ERROR("DPLL %d failed to lock\n", pipe);
>  
> -	I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
> -	POSTING_READ(DPLL_MD(crtc->pipe));
> +	I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
> +	POSTING_READ(DPLL_MD(pipe));
>  
>  	/* We do this three times for luck */
>  	I915_WRITE(reg, dpll);
> @@ -1608,11 +1609,11 @@ static void chv_enable_pll(struct intel_crtc *crtc,
>  {
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = dev->dev_private;
> -	int pipe = crtc->pipe;
> +	enum pipe pipe = crtc->pipe;
>  	enum dpio_channel port = vlv_pipe_to_channel(pipe);
>  	u32 tmp;
>  
> -	assert_pipe_disabled(dev_priv, crtc->pipe);
> +	assert_pipe_disabled(dev_priv, pipe);
>  
>  	mutex_lock(&dev_priv->sb_lock);

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2016-03-16  9:03 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-15 14:39 [PATCH 00/16] drm/i915: DSI and DPLL stuff for VLV/CHV mostly ville.syrjala
2016-03-15 14:39 ` [PATCH 01/16] drm/i915: Throw out BUGs from DPLL/PCH functions ville.syrjala
2016-03-16  9:02   ` Jani Nikula
2016-03-15 14:39 ` [PATCH 02/16] drm/i915: Make {vlv, chv}_{disable, update}_pll() more similar ville.syrjala
2016-03-30 13:31   ` Jani Nikula
2016-04-01 19:59     ` Ville Syrjälä
2016-03-15 14:39 ` [PATCH 03/16] drm/i915: Implement WaPixelRepeatModeFixForC0:chv ville.syrjala
2016-03-16  9:27   ` Jani Nikula
2016-03-16 13:07     ` Ville Syrjälä
2016-03-15 14:39 ` [PATCH 04/16] drm/i915: Add a local pipe variable to vlv_enable_pll() ville.syrjala
2016-03-16  9:03   ` Jani Nikula [this message]
2016-03-15 14:39 ` [PATCH 05/16] drm/i915: assert_panel_unlocked() in chv_enable_pll() ville.syrjala
2016-03-16  9:04   ` Jani Nikula
2016-03-15 14:39 ` [PATCH 06/16] drm/i915: Remove the "three times for luck" trick from vlv_enable_pll() ville.syrjala
2016-03-16  9:05   ` Jani Nikula
2016-04-01 19:58     ` Ville Syrjälä
2016-03-15 14:40 ` [PATCH 07/16] drm/i915: Setup DPLL/DPLLMD for DSI too on VLV/CHV ville.syrjala
2016-03-15 14:40 ` [PATCH 08/16] drm/i915: Don't read out port_clock on CHV when DPLL is disabled ville.syrjala
2016-03-16  9:06   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 09/16] drm/i915: Change lfsr_converts[] to u16 ville.syrjala
2016-03-16  8:42   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 10/16] drm/i915: Power down the DSI PLL before reconfiguring it ville.syrjala
2016-03-16  8:45   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 11/16] drm/i915: Compute DSI PLL parameters during .compute_config() ville.syrjala
2016-03-16  8:56   ` Jani Nikula
2016-03-16 12:59     ` Ville Syrjälä
2016-03-15 14:40 ` [PATCH 12/16] drm/i915: Fix CHV DSI PLL refclk during state readout ville.syrjala
2016-03-16  8:58   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 13/16] drm/i915: Eliminate {vlv, bxt}_configure_dsi_pll() ville.syrjala
2016-03-16  8:59   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 14/16] drm/i915: Dump pfit PGM_RATIOS as hex ville.syrjala
2016-03-16  9:00   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 15/16] drm/i915: Hook up pfit for DSI ville.syrjala
2016-03-30 13:35   ` Jani Nikula
2016-03-15 14:40 ` [PATCH 16/16] drm/i915: Reject 'Center' scaling mode for eDP/DSI on GMCH platforms ville.syrjala
2016-03-30 13:36   ` Jani Nikula
2016-03-15 15:27 ` ✗ Fi.CI.BAT: failure for drm/i915: DSI and DPLL stuff for VLV/CHV mostly Patchwork
2016-04-01 19:12   ` Ville Syrjälä
2016-04-01 19:39     ` Chris Wilson
2016-04-01 19:47       ` Ville Syrjälä
2016-04-01 19:53         ` Chris Wilson
2016-04-12 18:39 ` [PATCH 00/16] " Ville Syrjälä

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