Re: [PATCH 57/62] drm/i915/bdw: BWGTLB clock gate disable

Jesse Barnes
2013-11-05T17:21:58Z

On Sat, 2 Nov 2013 21:07:55 -0700
Ben Widawsky <benjamin.widawsky@intel.com> wrote:

> From: Ben Widawsky <ben@bwidawsk.net>
>
> Wa???
>
> Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 ++
> 2 files changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9608f96..2d16363 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -656,6 +656,7 @@
> #define ARB_MODE_SWIZZLE_SNB (1<<4)
> #define ARB_MODE_SWIZZLE_IVB (1<<5)
> #define GAMTARBMODE 0x04a08
> +#define ARB_MODE_BWGTLB_DISABLE (1<<9)
> #define ARB_MODE_SWIZZLE_BDW (1<<1)
> #define RENDER_HWS_PGA_GEN7 (0x04080)
> #define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 63f6e59..e6e12e1 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5286,6 +5286,8 @@ static void gen8_init_clock_gating(struct drm_device *dev)
> I915_WRITE(WM2_LP_ILK, 0);
> I915_WRITE(WM1_LP_ILK, 0);
>
> + I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
> +
> /* WaSwitchSolVfFArbitrationPriority */
> I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
>

We really need some rev checking for workarounds like these that don't
apply to every version, or I'm afraid we'll forget them, like we've
done on previous gens (not that it's particularly critical for simple
clock gating ones like this, but for perf critical ones it can be).

Otherwise,
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

--
Jesse Barnes, Intel Open Source Technology Center