Re: [PATCH 38/62] drm/i915/bdw: get the correct LCPLL frequency on Broadwell

Ville Syrjälä
2013-11-03T11:07:37Z

On Sat, Nov 02, 2013 at 09:07:36PM -0700, Ben Widawsky wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> v2: Rebased onto Paulo's MHz->kHz change.
>
> v3: Rebased on top of the Haswell pc8+ adjustements.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1)
> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> drivers/gpu/drm/i915/intel_ddi.c | 25 ++++++++++++++++++-------
> 2 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 68b877d..d5995dd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5282,6 +5282,9 @@
> #define LCPLL_PLL_LOCK (1<<30)
> #define LCPLL_CLK_FREQ_MASK (3<<26)
> #define LCPLL_CLK_FREQ_450 (0<<26)
> +#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
> +#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
> +#define LCPLL_CLK_FREQ_675_BDW (3<<26)
> #define LCPLL_CD_CLOCK_DISABLE (1<<25)
> #define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
> #define LCPLL_POWER_DOWN_ALLOW (1<<22)
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 31f4fe2..d464fd2 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1156,18 +1156,29 @@ static void intel_disable_ddi(struct intel_encoder *intel_encoder)
>
> int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv)
> {
> + struct drm_device *dev = dev_priv->dev;
> uint32_t lcpll = I915_READ(LCPLL_CTL);
> + uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
>
> - if (lcpll & LCPLL_CD_SOURCE_FCLK)
> + if (lcpll & LCPLL_CD_SOURCE_FCLK) {
> return 800000;

I couldn't find this 800 MHz number anywhere, even in HSW docs. But
I guess it doesn't really matter since fclk shouldn't be selected
for normal operation.

> - else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT)
> + } else if (I915_READ(HSW_FUSE_STRAP) & HSW_CDCLK_LIMIT) {
> return 450000;

I think this is actually incorrect for even HSW. The strap only tells
you what is allowed, but it doesn't affect the actual frequency. You
could still select the alternate frequencies, even though you shouldn't.

> - else if ((lcpll & LCPLL_CLK_FREQ_MASK) == LCPLL_CLK_FREQ_450)
> + } else if (freq == LCPLL_CLK_FREQ_450) {
> return 450000;
> - else if (IS_ULT(dev_priv->dev))
> - return 337500;
> - else
> - return 540000;
> + } else if (IS_HASWELL(dev)) {
> + if (IS_ULT(dev))
> + return 338000;
> + else
> + return 540000;
> + } else {
> + if (freq == LCPLL_CLK_FREQ_54O_BDW)
> + return 540000;
> + else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
> + return 338000;

337500

> + else
> + return 675000;
> + }
> }
>
> void intel_ddi_pll_init(struct drm_device *dev)
> --
> 1.8.4.2
>
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--
Ville Syrjälä
Intel OTC