* [Intel-gfx] [PATCH 01/12] drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock()
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 02/12] drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock() Ville Syrjala
` (13 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
What intel_ddi_{enable,disable}_pipe_clock() actually do is
enable the clock to the transcoder, not the pipe. Rename
accordingly.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 4 ++--
drivers/gpu/drm/i915/display/intel_ddi.c | 20 ++++++++++----------
drivers/gpu/drm/i915/display/intel_ddi.h | 6 +++---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++--
4 files changed, 17 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 7267ffc7f539..d5bb02f0868d 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -260,7 +260,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
ilk_pfit_disable(old_crtc_state);
- intel_ddi_disable_pipe_clock(old_crtc_state);
+ intel_ddi_disable_transcoder_clock(old_crtc_state);
pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
@@ -300,7 +300,7 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state,
hsw_fdi_link_train(encoder, crtc_state);
- intel_ddi_enable_pipe_clock(encoder, crtc_state);
+ intel_ddi_enable_transcoder_clock(encoder, crtc_state);
}
static void hsw_enable_crt(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 254559abedfb..7f34c2b30073 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -948,8 +948,8 @@ static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
main_link_aux_power_domain_get(dig_port, crtc_state);
}
-void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state)
+void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -969,7 +969,7 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
}
}
-void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
+void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -2387,7 +2387,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* 7.a Configure Transcoder Clock Select to direct the Port clock to the
* Transcoder.
*/
- intel_ddi_enable_pipe_clock(encoder, crtc_state);
+ intel_ddi_enable_transcoder_clock(encoder, crtc_state);
if (HAS_DP20(dev_priv))
intel_ddi_config_transcoder_dp2(encoder, crtc_state);
@@ -2514,7 +2514,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
if (!is_mst)
- intel_ddi_enable_pipe_clock(encoder, crtc_state);
+ intel_ddi_enable_transcoder_clock(encoder, crtc_state);
intel_dsc_dp_pps_write(encoder, crtc_state);
}
@@ -2556,7 +2556,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
icl_program_mg_dp_mode(dig_port, crtc_state);
- intel_ddi_enable_pipe_clock(encoder, crtc_state);
+ intel_ddi_enable_transcoder_clock(encoder, crtc_state);
dig_port->set_infoframes(encoder,
crtc_state->has_infoframe,
@@ -2672,7 +2672,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
}
} else {
if (!is_mst)
- intel_ddi_disable_pipe_clock(old_crtc_state);
+ intel_ddi_disable_transcoder_clock(old_crtc_state);
}
intel_disable_ddi_buf(encoder, old_crtc_state);
@@ -2683,7 +2683,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
* transcoder"
*/
if (DISPLAY_VER(dev_priv) >= 12)
- intel_ddi_disable_pipe_clock(old_crtc_state);
+ intel_ddi_disable_transcoder_clock(old_crtc_state);
intel_pps_vdd_on(intel_dp);
intel_pps_off(intel_dp);
@@ -2709,12 +2709,12 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
old_crtc_state, old_conn_state);
if (DISPLAY_VER(dev_priv) < 12)
- intel_ddi_disable_pipe_clock(old_crtc_state);
+ intel_ddi_disable_transcoder_clock(old_crtc_state);
intel_disable_ddi_buf(encoder, old_crtc_state);
if (DISPLAY_VER(dev_priv) >= 12)
- intel_ddi_disable_pipe_clock(old_crtc_state);
+ intel_ddi_disable_transcoder_clock(old_crtc_state);
intel_display_power_put(dev_priv,
dig_port->ddi_io_power_domain,
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.h b/drivers/gpu/drm/i915/display/intel_ddi.h
index d39076facdce..361f6874dde5 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.h
+++ b/drivers/gpu/drm/i915/display/intel_ddi.h
@@ -52,9 +52,9 @@ bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe);
void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state);
-void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
- const struct intel_crtc_state *crtc_state);
-void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state);
+void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state);
void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 8b0e4defa3f1..5555f27993b2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -598,7 +598,7 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
* no clock to the transcoder"
*/
if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
- intel_ddi_disable_pipe_clock(old_crtc_state);
+ intel_ddi_disable_transcoder_clock(old_crtc_state);
intel_mst->connector = NULL;
@@ -678,7 +678,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
* here for the following ones.
*/
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
- intel_ddi_enable_pipe_clock(encoder, pipe_config);
+ intel_ddi_enable_transcoder_clock(encoder, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 02/12] drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock()
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 01/12] drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock() Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 03/12] drm/i915: Give CPU transcoder timing registers TRANS_ prefix Ville Syrjala
` (12 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use an early return to get rid of the extra indentation level
in intel_ddi_{enable,disable}_transcoder_clock().
Also unify the platform handling in between the two while at
it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 39 ++++++++++++------------
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 7f34c2b30073..a30175022621 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -957,33 +957,34 @@ void intel_ddi_enable_transcoder_clock(struct intel_encoder *encoder,
enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
u32 val;
- if (cpu_transcoder != TRANSCODER_EDP) {
- if (DISPLAY_VER(dev_priv) >= 13)
- val = TGL_TRANS_CLK_SEL_PORT(phy);
- else if (DISPLAY_VER(dev_priv) >= 12)
- val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
- else
- val = TRANS_CLK_SEL_PORT(encoder->port);
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return;
- intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
- }
+ if (DISPLAY_VER(dev_priv) >= 13)
+ val = TGL_TRANS_CLK_SEL_PORT(phy);
+ else if (DISPLAY_VER(dev_priv) >= 12)
+ val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
+ else
+ val = TRANS_CLK_SEL_PORT(encoder->port);
+
+ intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
}
void intel_ddi_disable_transcoder_clock(const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val;
- if (cpu_transcoder != TRANSCODER_EDP) {
- if (DISPLAY_VER(dev_priv) >= 12)
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TGL_TRANS_CLK_SEL_DISABLED);
- else
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_DISABLED);
- }
+ if (cpu_transcoder == TRANSCODER_EDP)
+ return;
+
+ if (DISPLAY_VER(dev_priv) >= 12)
+ val = TGL_TRANS_CLK_SEL_DISABLED;
+ else
+ val = TRANS_CLK_SEL_DISABLED;
+
+ intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
}
static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 03/12] drm/i915: Give CPU transcoder timing registers TRANS_ prefix
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 01/12] drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock() Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 02/12] drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock() Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/ Ville Syrjala
` (11 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Name the CPU transcoder timing registers TRANS_FOO rather than
just FOO. This is the modern name, after the pipe/transcoder split
happened. Makes it a bit more obvious whether you pass in a pipe or
a transcoder.
PIPESRC is a bit special as it's a pipe register, even though it
lives in the transcoder registers range (0x60000 instead of 0x70000).
And BCLRPAT I suppose is a transcoder register (since it has something
to do with the timing generator), but it doesn't even exist after gen4
so I left it to use the only name it ever had in bspec.
And while at it let's pass in the correct enum in few more
places why don't we. Although in all those places the distinction
doesn't matter.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 12 +--
drivers/gpu/drm/i915/display/intel_crt.c | 19 ++--
drivers/gpu/drm/i915/display/intel_display.c | 49 ++++++-----
.../gpu/drm/i915/display/intel_pch_display.c | 14 +--
drivers/gpu/drm/i915/display/intel_psr.c | 6 +-
drivers/gpu/drm/i915/gvt/handlers.c | 4 +-
drivers/gpu/drm/i915/i915_reg.h | 88 +++++++++----------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 62 ++++++-------
8 files changed, 128 insertions(+), 126 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 05e749861658..e1fe59ca0892 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -887,7 +887,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
/* program TRANS_HTOTAL register */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, HTOTAL(dsi_trans),
+ intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
(hactive - 1) | ((htotal - 1) << 16));
}
@@ -910,7 +910,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, HSYNC(dsi_trans),
+ intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
(hsync_start - 1) | ((hsync_end - 1) << 16));
}
}
@@ -924,7 +924,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* struct drm_display_mode.
* For interlace mode: program required pixel minus 2
*/
- intel_de_write(dev_priv, VTOTAL(dsi_trans),
+ intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
(vactive - 1) | ((vtotal - 1) << 16));
}
@@ -938,7 +938,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (is_vid_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, VSYNC(dsi_trans),
+ intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
(vsync_start - 1) | ((vsync_end - 1) << 16));
}
}
@@ -952,7 +952,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (is_vid_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, VSYNCSHIFT(dsi_trans),
+ intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),
vsync_shift);
}
}
@@ -961,7 +961,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (DISPLAY_VER(dev_priv) >= 12) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, VBLANK(dsi_trans),
+ intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
(vactive - 1) | ((vtotal - 1) << 16));
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index d5bb02f0868d..4b7f8cd416fe 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -678,10 +678,11 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
}
static enum drm_connector_status
-intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
+intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
{
struct drm_device *dev = crt->base.base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
+ enum transcoder cpu_transcoder = (enum transcoder)pipe;
u32 save_bclrpat;
u32 save_vtotal;
u32 vtotal, vactive;
@@ -693,9 +694,9 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
- save_bclrpat = intel_de_read(dev_priv, BCLRPAT(pipe));
- save_vtotal = intel_de_read(dev_priv, VTOTAL(pipe));
- vblank = intel_de_read(dev_priv, VBLANK(pipe));
+ save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
+ save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
+ vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
vactive = (save_vtotal & 0x7ff) + 1;
@@ -704,7 +705,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
vblank_end = ((vblank >> 16) & 0xfff) + 1;
/* Set the border color to purple. */
- intel_de_write(dev_priv, BCLRPAT(pipe), 0x500050);
+ intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
if (DISPLAY_VER(dev_priv) != 2) {
u32 pipeconf = intel_de_read(dev_priv, PIPECONF(pipe));
@@ -730,11 +731,11 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
- u32 vsync = intel_de_read(dev_priv, VSYNC(pipe));
+ u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
u32 vsync_start = (vsync & 0xffff) + 1;
vblank_start = vsync_start;
- intel_de_write(dev_priv, VBLANK(pipe),
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
(vblank_start - 1) | ((vblank_end - 1) << 16));
restore_vblank = true;
}
@@ -766,7 +767,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
/* restore vblank if necessary */
if (restore_vblank)
- intel_de_write(dev_priv, VBLANK(pipe), vblank);
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
/*
* If more than 3/4 of the scanline detected a monitor,
* then it is assumed to be present. This works even on i830,
@@ -779,7 +780,7 @@ intel_crt_load_detect(struct intel_crt *crt, u32 pipe)
}
/* Restore previous settings */
- intel_de_write(dev_priv, BCLRPAT(pipe), save_bclrpat);
+ intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
return status;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 322f3b2c741d..a93f3630e9f8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1848,7 +1848,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta
intel_set_transcoder_timings(crtc_state);
if (cpu_transcoder != TRANSCODER_EDP)
- intel_de_write(dev_priv, PIPE_MULT(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
crtc_state->pixel_multiplier - 1);
hsw_set_frame_start_delay(crtc_state);
@@ -2844,21 +2844,21 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
}
if (DISPLAY_VER(dev_priv) > 3)
- intel_de_write(dev_priv, VSYNCSHIFT(cpu_transcoder),
- vsyncshift);
+ intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
+ vsyncshift);
- intel_de_write(dev_priv, HTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
(adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
- intel_de_write(dev_priv, HBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
(adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
- intel_de_write(dev_priv, HSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
(adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
- intel_de_write(dev_priv, VTOTAL(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
(adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
- intel_de_write(dev_priv, VBLANK(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
(adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
- intel_de_write(dev_priv, VSYNC(cpu_transcoder),
+ intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
(adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
@@ -2867,8 +2867,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
* bits. */
if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
(pipe == PIPE_B || pipe == PIPE_C))
- intel_de_write(dev_priv, VTOTAL(pipe),
- intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
+ intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
+ intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
}
@@ -2910,33 +2910,33 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
u32 tmp;
- tmp = intel_de_read(dev_priv, HTOTAL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, HBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
pipe_config->hw.adjusted_mode.crtc_hblank_start =
(tmp & 0xffff) + 1;
pipe_config->hw.adjusted_mode.crtc_hblank_end =
((tmp >> 16) & 0xffff) + 1;
}
- tmp = intel_de_read(dev_priv, HSYNC(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
- tmp = intel_de_read(dev_priv, VTOTAL(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
- tmp = intel_de_read(dev_priv, VBLANK(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
pipe_config->hw.adjusted_mode.crtc_vblank_start =
(tmp & 0xffff) + 1;
pipe_config->hw.adjusted_mode.crtc_vblank_end =
((tmp >> 16) & 0xffff) + 1;
}
- tmp = intel_de_read(dev_priv, VSYNC(cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
@@ -4092,7 +4092,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
pipe_config->pixel_multiplier =
intel_de_read(dev_priv,
- PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
+ TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
} else {
pipe_config->pixel_multiplier = 1;
}
@@ -8791,6 +8791,7 @@ int intel_modeset_init(struct drm_i915_private *i915)
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
{
struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
+ enum transcoder cpu_transcoder = (enum transcoder)pipe;
/* 640x480@60Hz, ~25175 kHz */
struct dpll clock = {
.m1 = 18,
@@ -8817,12 +8818,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
PLL_REF_INPUT_DREFCLK |
DPLL_VCO_ENABLE;
- intel_de_write(dev_priv, HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16));
- intel_de_write(dev_priv, HBLANK(pipe), (640 - 1) | ((800 - 1) << 16));
- intel_de_write(dev_priv, HSYNC(pipe), (656 - 1) | ((752 - 1) << 16));
- intel_de_write(dev_priv, VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16));
- intel_de_write(dev_priv, VBLANK(pipe), (480 - 1) | ((525 - 1) << 16));
- intel_de_write(dev_priv, VSYNC(pipe), (490 - 1) | ((492 - 1) << 16));
+ intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
+ intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
+ intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), (656 - 1) | ((752 - 1) << 16));
+ intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
+ intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), (490 - 1) | ((492 - 1) << 16));
intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
intel_de_write(dev_priv, FP0(pipe), fp);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 419221f4b454..e55bc4763278 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -220,20 +220,20 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder),
- intel_de_read(dev_priv, HTOTAL(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder),
- intel_de_read(dev_priv, HBLANK(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder),
- intel_de_read(dev_priv, HSYNC(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder),
- intel_de_read(dev_priv, VTOTAL(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder),
- intel_de_read(dev_priv, VBLANK(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder),
- intel_de_read(dev_priv, VSYNC(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)));
intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder),
- intel_de_read(dev_priv, VSYNCSHIFT(cpu_transcoder)));
+ intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder)));
}
static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2954759e9d12..a021f59f0ac7 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1051,7 +1051,7 @@ void intel_psr_get_config(struct intel_encoder *encoder,
}
if (DISPLAY_VER(dev_priv) >= 12) {
- val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
+ val = intel_de_read(dev_priv, TRANS_EXITLINE(intel_dp->psr.transcoder));
val &= EXITLINE_MASK;
pipe_config->dc3co_exitline = val;
}
@@ -1132,11 +1132,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
* TODO: if future platforms supports DC3CO in more than one
* transcoder, EXITLINE will need to be unset when disabling PSR
*/
- val = intel_de_read(dev_priv, EXITLINE(cpu_transcoder));
+ val = intel_de_read(dev_priv, TRANS_EXITLINE(cpu_transcoder));
val &= ~EXITLINE_MASK;
val |= intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT;
val |= EXITLINE_ENABLE;
- intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val);
+ intel_de_write(dev_priv, TRANS_EXITLINE(cpu_transcoder), val);
}
if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv))
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 735fc83e7026..eed15fbc7069 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -666,8 +666,8 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu)
link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A));
/* Get H/V total from transcoder timing */
- htotal = (vgpu_vreg_t(vgpu, HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
- vtotal = (vgpu_vreg_t(vgpu, VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
+ htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT);
+ vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT);
if (dp_br && link_n && htotal && vtotal) {
u64 pixel_clk = 0;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 596efc940ee7..28b1226688b8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1911,48 +1911,48 @@
#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915)
#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
-/* Pipe A timing regs */
-#define _HTOTAL_A 0x60000
-#define _HBLANK_A 0x60004
-#define _HSYNC_A 0x60008
-#define _VTOTAL_A 0x6000c
-#define _VBLANK_A 0x60010
-#define _VSYNC_A 0x60014
-#define _EXITLINE_A 0x60018
-#define _PIPEASRC 0x6001c
+/* Pipe/transcoder A timing regs */
+#define _TRANS_HTOTAL_A 0x60000
+#define _TRANS_HBLANK_A 0x60004
+#define _TRANS_HSYNC_A 0x60008
+#define _TRANS_VTOTAL_A 0x6000c
+#define _TRANS_VBLANK_A 0x60010
+#define _TRANS_VSYNC_A 0x60014
+#define _TRANS_EXITLINE_A 0x60018
+#define _PIPEASRC 0x6001c
#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
#define PIPESRC_WIDTH(w) REG_FIELD_PREP(PIPESRC_WIDTH_MASK, (w))
#define PIPESRC_HEIGHT_MASK REG_GENMASK(15, 0)
#define PIPESRC_HEIGHT(h) REG_FIELD_PREP(PIPESRC_HEIGHT_MASK, (h))
-#define _BCLRPAT_A 0x60020
-#define _VSYNCSHIFT_A 0x60028
-#define _PIPE_MULT_A 0x6002c
+#define _BCLRPAT_A 0x60020
+#define _TRANS_VSYNCSHIFT_A 0x60028
+#define _TRANS_MULT_A 0x6002c
-/* Pipe B timing regs */
-#define _HTOTAL_B 0x61000
-#define _HBLANK_B 0x61004
-#define _HSYNC_B 0x61008
-#define _VTOTAL_B 0x6100c
-#define _VBLANK_B 0x61010
-#define _VSYNC_B 0x61014
-#define _PIPEBSRC 0x6101c
-#define _BCLRPAT_B 0x61020
-#define _VSYNCSHIFT_B 0x61028
-#define _PIPE_MULT_B 0x6102c
+/* Pipe/transcoder B timing regs */
+#define _TRANS_HTOTAL_B 0x61000
+#define _TRANS_HBLANK_B 0x61004
+#define _TRANS_HSYNC_B 0x61008
+#define _TRANS_VTOTAL_B 0x6100c
+#define _TRANS_VBLANK_B 0x61010
+#define _TRANS_VSYNC_B 0x61014
+#define _PIPEBSRC 0x6101c
+#define _BCLRPAT_B 0x61020
+#define _TRANS_VSYNCSHIFT_B 0x61028
+#define _TRANS_MULT_B 0x6102c
/* DSI 0 timing regs */
-#define _HTOTAL_DSI0 0x6b000
-#define _HSYNC_DSI0 0x6b008
-#define _VTOTAL_DSI0 0x6b00c
-#define _VSYNC_DSI0 0x6b014
-#define _VSYNCSHIFT_DSI0 0x6b028
+#define _TRANS_HTOTAL_DSI0 0x6b000
+#define _TRANS_HSYNC_DSI0 0x6b008
+#define _TRANS_VTOTAL_DSI0 0x6b00c
+#define _TRANS_VSYNC_DSI0 0x6b014
+#define _TRANS_VSYNCSHIFT_DSI0 0x6b028
/* DSI 1 timing regs */
-#define _HTOTAL_DSI1 0x6b800
-#define _HSYNC_DSI1 0x6b808
-#define _VTOTAL_DSI1 0x6b80c
-#define _VSYNC_DSI1 0x6b814
-#define _VSYNCSHIFT_DSI1 0x6b828
+#define _TRANS_HTOTAL_DSI1 0x6b800
+#define _TRANS_HSYNC_DSI1 0x6b808
+#define _TRANS_VTOTAL_DSI1 0x6b80c
+#define _TRANS_VSYNC_DSI1 0x6b814
+#define _TRANS_VSYNCSHIFT_DSI1 0x6b828
#define TRANSCODER_A_OFFSET 0x60000
#define TRANSCODER_B_OFFSET 0x61000
@@ -1963,18 +1963,18 @@
#define TRANSCODER_DSI0_OFFSET 0x6b000
#define TRANSCODER_DSI1_OFFSET 0x6b800
-#define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A)
-#define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A)
-#define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A)
-#define VTOTAL(trans) _MMIO_TRANS2(trans, _VTOTAL_A)
-#define VBLANK(trans) _MMIO_TRANS2(trans, _VBLANK_A)
-#define VSYNC(trans) _MMIO_TRANS2(trans, _VSYNC_A)
-#define BCLRPAT(trans) _MMIO_TRANS2(trans, _BCLRPAT_A)
-#define VSYNCSHIFT(trans) _MMIO_TRANS2(trans, _VSYNCSHIFT_A)
-#define PIPESRC(trans) _MMIO_TRANS2(trans, _PIPEASRC)
-#define PIPE_MULT(trans) _MMIO_TRANS2(trans, _PIPE_MULT_A)
+#define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A)
+#define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A)
+#define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A)
+#define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A)
+#define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A)
+#define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A)
+#define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A)
+#define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A)
+#define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC)
+#define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A)
-#define EXITLINE(trans) _MMIO_TRANS2(trans, _EXITLINE_A)
+#define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A)
#define EXITLINE_ENABLE REG_BIT(31)
#define EXITLINE_MASK REG_GENMASK(12, 0)
#define EXITLINE_SHIFT 0
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c5cdff38cc5a..d649ff2bb780 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -219,41 +219,41 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(SPRSCALE(PIPE_C));
MMIO_D(SPRSURFLIVE(PIPE_C));
MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0));
- MMIO_D(HTOTAL(TRANSCODER_A));
- MMIO_D(HBLANK(TRANSCODER_A));
- MMIO_D(HSYNC(TRANSCODER_A));
- MMIO_D(VTOTAL(TRANSCODER_A));
- MMIO_D(VBLANK(TRANSCODER_A));
- MMIO_D(VSYNC(TRANSCODER_A));
+ MMIO_D(TRANS_HTOTAL(TRANSCODER_A));
+ MMIO_D(TRANS_HBLANK(TRANSCODER_A));
+ MMIO_D(TRANS_HSYNC(TRANSCODER_A));
+ MMIO_D(TRANS_VTOTAL(TRANSCODER_A));
+ MMIO_D(TRANS_VBLANK(TRANSCODER_A));
+ MMIO_D(TRANS_VSYNC(TRANSCODER_A));
MMIO_D(BCLRPAT(TRANSCODER_A));
- MMIO_D(VSYNCSHIFT(TRANSCODER_A));
+ MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A));
MMIO_D(PIPESRC(TRANSCODER_A));
- MMIO_D(HTOTAL(TRANSCODER_B));
- MMIO_D(HBLANK(TRANSCODER_B));
- MMIO_D(HSYNC(TRANSCODER_B));
- MMIO_D(VTOTAL(TRANSCODER_B));
- MMIO_D(VBLANK(TRANSCODER_B));
- MMIO_D(VSYNC(TRANSCODER_B));
+ MMIO_D(TRANS_HTOTAL(TRANSCODER_B));
+ MMIO_D(TRANS_HBLANK(TRANSCODER_B));
+ MMIO_D(TRANS_HSYNC(TRANSCODER_B));
+ MMIO_D(TRANS_VTOTAL(TRANSCODER_B));
+ MMIO_D(TRANS_VBLANK(TRANSCODER_B));
+ MMIO_D(TRANS_VSYNC(TRANSCODER_B));
MMIO_D(BCLRPAT(TRANSCODER_B));
- MMIO_D(VSYNCSHIFT(TRANSCODER_B));
+ MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B));
MMIO_D(PIPESRC(TRANSCODER_B));
- MMIO_D(HTOTAL(TRANSCODER_C));
- MMIO_D(HBLANK(TRANSCODER_C));
- MMIO_D(HSYNC(TRANSCODER_C));
- MMIO_D(VTOTAL(TRANSCODER_C));
- MMIO_D(VBLANK(TRANSCODER_C));
- MMIO_D(VSYNC(TRANSCODER_C));
+ MMIO_D(TRANS_HTOTAL(TRANSCODER_C));
+ MMIO_D(TRANS_HBLANK(TRANSCODER_C));
+ MMIO_D(TRANS_HSYNC(TRANSCODER_C));
+ MMIO_D(TRANS_VTOTAL(TRANSCODER_C));
+ MMIO_D(TRANS_VBLANK(TRANSCODER_C));
+ MMIO_D(TRANS_VSYNC(TRANSCODER_C));
MMIO_D(BCLRPAT(TRANSCODER_C));
- MMIO_D(VSYNCSHIFT(TRANSCODER_C));
+ MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C));
MMIO_D(PIPESRC(TRANSCODER_C));
- MMIO_D(HTOTAL(TRANSCODER_EDP));
- MMIO_D(HBLANK(TRANSCODER_EDP));
- MMIO_D(HSYNC(TRANSCODER_EDP));
- MMIO_D(VTOTAL(TRANSCODER_EDP));
- MMIO_D(VBLANK(TRANSCODER_EDP));
- MMIO_D(VSYNC(TRANSCODER_EDP));
+ MMIO_D(TRANS_HTOTAL(TRANSCODER_EDP));
+ MMIO_D(TRANS_HBLANK(TRANSCODER_EDP));
+ MMIO_D(TRANS_HSYNC(TRANSCODER_EDP));
+ MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP));
+ MMIO_D(TRANS_VBLANK(TRANSCODER_EDP));
+ MMIO_D(TRANS_VSYNC(TRANSCODER_EDP));
MMIO_D(BCLRPAT(TRANSCODER_EDP));
- MMIO_D(VSYNCSHIFT(TRANSCODER_EDP));
+ MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP));
MMIO_D(PIPE_DATA_M1(TRANSCODER_A));
MMIO_D(PIPE_DATA_N1(TRANSCODER_A));
MMIO_D(PIPE_DATA_M2(TRANSCODER_A));
@@ -494,9 +494,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(GAMMA_MODE(PIPE_A));
MMIO_D(GAMMA_MODE(PIPE_B));
MMIO_D(GAMMA_MODE(PIPE_C));
- MMIO_D(PIPE_MULT(PIPE_A));
- MMIO_D(PIPE_MULT(PIPE_B));
- MMIO_D(PIPE_MULT(PIPE_C));
+ MMIO_D(TRANS_MULT(TRANSCODER_A));
+ MMIO_D(TRANS_MULT(TRANSCODER_B));
+ MMIO_D(TRANS_MULT(TRANSCODER_C));
MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A));
MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B));
MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C));
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (2 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 03/12] drm/i915: Give CPU transcoder timing registers TRANS_ prefix Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-14 10:05 ` Jani Nikula
2023-02-13 22:52 ` [Intel-gfx] [PATCH 05/12] drm/i915: Dump blanking start/end Ville Syrjala
` (10 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename PIPECONF to TRANSCONF to make it clear what it actually
applies to.
While the usual convention is to pick the earliers name I think
in this case it's more clear to use the later name. Especially
as even the register offset is in the wrong range (0x70000 vs.
0x60000) and thus makes it look like this is per-pipe.
There is one place in gvt that's doing something with TRANSCONF
while iterating with for_each_pipe(). So that might not be doing
the right thing for TRANSCODER_EDP, dunno. Not knowing what it
does I left it as is to avoid breakage.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 16 +-
drivers/gpu/drm/i915/display/intel_crt.c | 10 +-
drivers/gpu/drm/i915/display/intel_display.c | 171 +++++++++---------
.../i915/display/intel_display_power_well.c | 8 +-
drivers/gpu/drm/i915/display/intel_drrs.c | 8 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 8 +-
.../gpu/drm/i915/display/intel_pch_display.c | 16 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
drivers/gpu/drm/i915/gvt/display.c | 16 +-
drivers/gpu/drm/i915/gvt/handlers.c | 14 +-
drivers/gpu/drm/i915/i915_reg.h | 106 +++++------
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 +-
12 files changed, 192 insertions(+), 191 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index e1fe59ca0892..07897d6f9c53 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -976,11 +976,11 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv, PIPECONF(dsi_trans), 0, PIPECONF_ENABLE);
+ intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE);
/* wait for transcoder to be enabled */
- if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
- PIPECONF_STATE_ENABLE, 10))
+ if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
+ TRANSCONF_STATE_ENABLE, 10))
drm_err(&dev_priv->drm,
"DSI transcoder not enabled\n");
}
@@ -1238,11 +1238,11 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
dsi_trans = dsi_port_to_transcoder(port);
/* disable transcoder */
- intel_de_rmw(dev_priv, PIPECONF(dsi_trans), PIPECONF_ENABLE, 0);
+ intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0);
/* wait for transcoder to be disabled */
- if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
- PIPECONF_STATE_ENABLE, 50))
+ if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
+ TRANSCONF_STATE_ENABLE, 50))
drm_err(&dev_priv->drm,
"DSI trancoder not disabled\n");
}
@@ -1662,8 +1662,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
goto out;
}
- tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
- ret = tmp & PIPECONF_ENABLE;
+ tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));
+ ret = tmp & TRANSCONF_ENABLE;
}
out:
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 4b7f8cd416fe..ef0c7f5b0ad6 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -708,11 +708,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
if (DISPLAY_VER(dev_priv) != 2) {
- u32 pipeconf = intel_de_read(dev_priv, PIPECONF(pipe));
+ u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
- intel_de_write(dev_priv, PIPECONF(pipe),
- pipeconf | PIPECONF_FORCE_BORDER);
- intel_de_posting_read(dev_priv, PIPECONF(pipe));
+ intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
+ transconf | TRANSCONF_FORCE_BORDER);
+ intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
/* Wait for next Vblank to substitue
* border color for Color info */
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
@@ -721,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
connector_status_connected :
connector_status_disconnected;
- intel_de_write(dev_priv, PIPECONF(pipe), pipeconf);
+ intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
} else {
bool restore_vblank = false;
int count, detect;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a93f3630e9f8..0aca842df8f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -396,8 +396,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
/* Wait for the Pipe State to go off */
- if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
- PIPECONF_STATE_ENABLE, 100))
+ if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
+ TRANSCONF_STATE_ENABLE, 100))
drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
} else {
intel_wait_for_pipe_scanline_stopped(crtc);
@@ -418,8 +418,8 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
if (wakeref) {
- u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
- cur_state = !!(val & PIPECONF_ENABLE);
+ u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+ cur_state = !!(val & TRANSCONF_ENABLE);
intel_display_power_put(dev_priv, power_domain, wakeref);
} else {
@@ -531,15 +531,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
0, PIPE_ARB_USE_PROG_SLOTS);
- reg = PIPECONF(cpu_transcoder);
+ reg = TRANSCONF(cpu_transcoder);
val = intel_de_read(dev_priv, reg);
- if (val & PIPECONF_ENABLE) {
+ if (val & TRANSCONF_ENABLE) {
/* we keep both pipes enabled on 830 */
drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
return;
}
- intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
+ intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
intel_de_posting_read(dev_priv, reg);
/*
@@ -570,9 +570,9 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
*/
assert_planes_disabled(crtc);
- reg = PIPECONF(cpu_transcoder);
+ reg = TRANSCONF(cpu_transcoder);
val = intel_de_read(dev_priv, reg);
- if ((val & PIPECONF_ENABLE) == 0)
+ if ((val & TRANSCONF_ENABLE) == 0)
return;
/*
@@ -580,11 +580,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
* so best keep it disabled when not needed.
*/
if (old_crtc_state->double_wide)
- val &= ~PIPECONF_DOUBLE_WIDE;
+ val &= ~TRANSCONF_DOUBLE_WIDE;
/* Don't disable pipe or pipe PLLs if needed */
if (!IS_I830(dev_priv))
- val &= ~PIPECONF_ENABLE;
+ val &= ~TRANSCONF_ENABLE;
if (DISPLAY_VER(dev_priv) >= 14)
intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
@@ -594,7 +594,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
intel_de_write(dev_priv, reg, val);
- if ((val & PIPECONF_ENABLE) == 0)
+ if ((val & TRANSCONF_ENABLE) == 0)
intel_wait_for_pipe_off(old_crtc_state);
}
@@ -2897,9 +2897,9 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
if (DISPLAY_VER(dev_priv) >= 9 ||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
- return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
+ return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
else
- return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
+ return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
}
static void intel_get_transcoder_timings(struct intel_crtc *crtc,
@@ -2984,7 +2984,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- u32 pipeconf = 0;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ u32 val = 0;
/*
* - We keep both pipes enabled on 830
@@ -2992,18 +2993,18 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
* - During fastset the pipe is already enabled and must remain so
*/
if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
- pipeconf |= PIPECONF_ENABLE;
+ val |= TRANSCONF_ENABLE;
if (crtc_state->double_wide)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
+ val |= TRANSCONF_DOUBLE_WIDE;
/* only g4x and later have fancy bpc/dither controls */
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) {
/* Bspec claims that we can't use dithering for 30bpp pipes. */
if (crtc_state->dither && crtc_state->pipe_bpp != 30)
- pipeconf |= PIPECONF_DITHER_EN |
- PIPECONF_DITHER_TYPE_SP;
+ val |= TRANSCONF_DITHER_EN |
+ TRANSCONF_DITHER_TYPE_SP;
switch (crtc_state->pipe_bpp) {
default:
@@ -3011,13 +3012,13 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
MISSING_CASE(crtc_state->pipe_bpp);
fallthrough;
case 18:
- pipeconf |= PIPECONF_BPC_6;
+ val |= TRANSCONF_BPC_6;
break;
case 24:
- pipeconf |= PIPECONF_BPC_8;
+ val |= TRANSCONF_BPC_8;
break;
case 30:
- pipeconf |= PIPECONF_BPC_10;
+ val |= TRANSCONF_BPC_10;
break;
}
}
@@ -3025,23 +3026,23 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
if (DISPLAY_VER(dev_priv) < 4 ||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
- pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
else
- pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
+ val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
} else {
- pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
+ val |= TRANSCONF_INTERLACE_PROGRESSIVE;
}
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
crtc_state->limited_color_range)
- pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
+ val |= TRANSCONF_COLOR_RANGE_SELECT;
- pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
- pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
+ val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
- intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
- intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
+ intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
+ intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
}
static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
@@ -3200,20 +3201,20 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
ret = false;
- tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
- if (!(tmp & PIPECONF_ENABLE))
+ tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+ if (!(tmp & TRANSCONF_ENABLE))
goto out;
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) {
- switch (tmp & PIPECONF_BPC_MASK) {
- case PIPECONF_BPC_6:
+ switch (tmp & TRANSCONF_BPC_MASK) {
+ case TRANSCONF_BPC_6:
pipe_config->pipe_bpp = 18;
break;
- case PIPECONF_BPC_8:
+ case TRANSCONF_BPC_8:
pipe_config->pipe_bpp = 24;
break;
- case PIPECONF_BPC_10:
+ case TRANSCONF_BPC_10:
pipe_config->pipe_bpp = 30;
break;
default:
@@ -3223,12 +3224,12 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
}
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
- (tmp & PIPECONF_COLOR_RANGE_SELECT))
+ (tmp & TRANSCONF_COLOR_RANGE_SELECT))
pipe_config->limited_color_range = true;
- pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
+ pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
- pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
+ pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
if (IS_CHERRYVIEW(dev_priv))
pipe_config->cgm_mode = intel_de_read(dev_priv,
@@ -3238,7 +3239,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
intel_color_get_config(pipe_config);
if (DISPLAY_VER(dev_priv) < 4)
- pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
+ pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
intel_get_transcoder_timings(crtc, pipe_config);
intel_get_pipe_src_size(crtc, pipe_config);
@@ -3308,7 +3309,7 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum pipe pipe = crtc->pipe;
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
u32 val = 0;
/*
@@ -3316,7 +3317,7 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
* - During fastset the pipe is already enabled and must remain so
*/
if (!intel_crtc_needs_modeset(crtc_state))
- val |= PIPECONF_ENABLE;
+ val |= TRANSCONF_ENABLE;
switch (crtc_state->pipe_bpp) {
default:
@@ -3324,26 +3325,26 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
MISSING_CASE(crtc_state->pipe_bpp);
fallthrough;
case 18:
- val |= PIPECONF_BPC_6;
+ val |= TRANSCONF_BPC_6;
break;
case 24:
- val |= PIPECONF_BPC_8;
+ val |= TRANSCONF_BPC_8;
break;
case 30:
- val |= PIPECONF_BPC_10;
+ val |= TRANSCONF_BPC_10;
break;
case 36:
- val |= PIPECONF_BPC_12;
+ val |= TRANSCONF_BPC_12;
break;
}
if (crtc_state->dither)
- val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
+ val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- val |= PIPECONF_INTERLACE_IF_ID_ILK;
+ val |= TRANSCONF_INTERLACE_IF_ID_ILK;
else
- val |= PIPECONF_INTERLACE_PF_PD_ILK;
+ val |= TRANSCONF_INTERLACE_PF_PD_ILK;
/*
* This would end up with an odd purple hue over
@@ -3354,18 +3355,18 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
if (crtc_state->limited_color_range &&
!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
- val |= PIPECONF_COLOR_RANGE_SELECT;
+ val |= TRANSCONF_COLOR_RANGE_SELECT;
if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
- val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
+ val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
- val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
+ val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
- val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
- val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
+ val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
+ val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
- intel_de_write(dev_priv, PIPECONF(pipe), val);
- intel_de_posting_read(dev_priv, PIPECONF(pipe));
+ intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
+ intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
}
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
@@ -3380,22 +3381,22 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
* - During fastset the pipe is already enabled and must remain so
*/
if (!intel_crtc_needs_modeset(crtc_state))
- val |= PIPECONF_ENABLE;
+ val |= TRANSCONF_ENABLE;
if (IS_HASWELL(dev_priv) && crtc_state->dither)
- val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
+ val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- val |= PIPECONF_INTERLACE_IF_ID_ILK;
+ val |= TRANSCONF_INTERLACE_IF_ID_ILK;
else
- val |= PIPECONF_INTERLACE_PF_PD_ILK;
+ val |= TRANSCONF_INTERLACE_PF_PD_ILK;
if (IS_HASWELL(dev_priv) &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
- val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
+ val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
- intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
- intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
+ intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
+ intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
}
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
@@ -3620,33 +3621,33 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
pipe_config->shared_dpll = NULL;
ret = false;
- tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
- if (!(tmp & PIPECONF_ENABLE))
+ tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
+ if (!(tmp & TRANSCONF_ENABLE))
goto out;
- switch (tmp & PIPECONF_BPC_MASK) {
- case PIPECONF_BPC_6:
+ switch (tmp & TRANSCONF_BPC_MASK) {
+ case TRANSCONF_BPC_6:
pipe_config->pipe_bpp = 18;
break;
- case PIPECONF_BPC_8:
+ case TRANSCONF_BPC_8:
pipe_config->pipe_bpp = 24;
break;
- case PIPECONF_BPC_10:
+ case TRANSCONF_BPC_10:
pipe_config->pipe_bpp = 30;
break;
- case PIPECONF_BPC_12:
+ case TRANSCONF_BPC_12:
pipe_config->pipe_bpp = 36;
break;
default:
break;
}
- if (tmp & PIPECONF_COLOR_RANGE_SELECT)
+ if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
pipe_config->limited_color_range = true;
- switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
- case PIPECONF_OUTPUT_COLORSPACE_YUV601:
- case PIPECONF_OUTPUT_COLORSPACE_YUV709:
+ switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
+ case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
+ case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
break;
default:
@@ -3654,11 +3655,11 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
break;
}
- pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
+ pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
- pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
+ pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
- pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
+ pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
pipe_config->csc_mode = intel_de_read(dev_priv,
PIPE_CSC_MODE(crtc->pipe));
@@ -3935,9 +3936,9 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
pipe_config->pch_pfit.force_thru = true;
}
- tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
+ tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
- return tmp & PIPECONF_ENABLE;
+ return tmp & TRANSCONF_ENABLE;
}
static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
@@ -4041,9 +4042,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
if (IS_HASWELL(dev_priv)) {
u32 tmp = intel_de_read(dev_priv,
- PIPECONF(pipe_config->cpu_transcoder));
+ TRANSCONF(pipe_config->cpu_transcoder));
- if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
+ if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
else
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
@@ -8855,8 +8856,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
udelay(150); /* wait for warmup */
}
- intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
- intel_de_posting_read(dev_priv, PIPECONF(pipe));
+ intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
+ intel_de_posting_read(dev_priv, TRANSCONF(pipe));
intel_wait_for_pipe_scanline_moving(crtc);
}
@@ -8879,8 +8880,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
drm_WARN_ON(&dev_priv->drm,
intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
- intel_de_write(dev_priv, PIPECONF(pipe), 0);
- intel_de_posting_read(dev_priv, PIPECONF(pipe));
+ intel_de_write(dev_priv, TRANSCONF(pipe), 0);
+ intel_de_posting_read(dev_priv, TRANSCONF(pipe));
intel_wait_for_pipe_scanline_stopped(crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8710dd41ffd4..b34851e42614 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1033,9 +1033,9 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
+ if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
i830_enable_pipe(dev_priv, PIPE_A);
- if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
+ if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
i830_enable_pipe(dev_priv, PIPE_B);
}
@@ -1049,8 +1049,8 @@ static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
- intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
+ return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
+ intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
}
static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
index 29c6421cd666..fe4c531a2574 100644
--- a/drivers/gpu/drm/i915/display/intel_drrs.c
+++ b/drivers/gpu/drm/i915/display/intel_drrs.c
@@ -71,18 +71,18 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc,
u32 val, bit;
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- bit = PIPECONF_REFRESH_RATE_ALT_VLV;
+ bit = TRANSCONF_REFRESH_RATE_ALT_VLV;
else
- bit = PIPECONF_REFRESH_RATE_ALT_ILK;
+ bit = TRANSCONF_REFRESH_RATE_ALT_ILK;
- val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
+ val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
if (refresh_rate == DRRS_REFRESH_RATE_LOW)
val |= bit;
else
val &= ~bit;
- intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
+ intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
}
static void
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index f62d9a931349..091d4d36d9de 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -902,7 +902,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
temp = intel_de_read(dev_priv, reg);
temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
- temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
+ temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
intel_de_posting_read(dev_priv, reg);
@@ -958,7 +958,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
reg = FDI_RX_CTL(pipe);
temp = intel_de_read(dev_priv, reg);
temp &= ~(0x7 << 16);
- temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
+ temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
intel_de_posting_read(dev_priv, reg);
@@ -982,9 +982,9 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
temp &= ~FDI_LINK_TRAIN_NONE;
temp |= FDI_LINK_TRAIN_PATTERN_1;
}
- /* BPC in FDI rx is consistent with that in PIPECONF */
+ /* BPC in FDI rx is consistent with that in TRANSCONF */
temp &= ~(0x07 << 16);
- temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
+ temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
intel_de_write(dev_priv, reg, temp);
intel_de_posting_read(dev_priv, reg);
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index e55bc4763278..c1d336f39770 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -267,7 +267,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
reg = PCH_TRANSCONF(pipe);
val = intel_de_read(dev_priv, reg);
- pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
+ pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe));
if (HAS_PCH_IBX(dev_priv)) {
/* Configure frame start delay to match the CPU */
@@ -279,15 +279,15 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
* that in pipeconf reg. For HDMI we must use 8bpc
* here for both 8bpc and 12bpc.
*/
- val &= ~PIPECONF_BPC_MASK;
+ val &= ~TRANSCONF_BPC_MASK;
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
- val |= PIPECONF_BPC_8;
+ val |= TRANSCONF_BPC_8;
else
- val |= pipeconf_val & PIPECONF_BPC_MASK;
+ val |= pipeconf_val & TRANSCONF_BPC_MASK;
}
val &= ~TRANS_INTERLACE_MASK;
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
+ if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {
if (HAS_PCH_IBX(dev_priv) &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
@@ -415,7 +415,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
intel_crtc_has_dp_encoder(crtc_state)) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
- u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
+ u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5;
i915_reg_t reg = TRANS_DP_CTL(pipe);
enum port port;
@@ -566,9 +566,9 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
val = TRANS_ENABLE;
- pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
+ pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
- if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
+ if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
val |= TRANS_INTERLACE_INTERLACED;
else
val |= TRANS_INTERLACE_PROGRESSIVE;
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index 2c945a949ad2..8d2e6e151ba0 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -1000,7 +1000,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
*/
if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
port == PORT_C)
- enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
+ enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
/* Try command mode if video mode not enabled */
if (!enabled) {
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 4d898b14de93..e0c5dfb788eb 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -63,7 +63,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
{
struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
- if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
+ if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE))
return 0;
if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
@@ -79,7 +79,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
pipe < PIPE_A || pipe >= I915_MAX_PIPES))
return -EINVAL;
- if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
+ if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE)
return 1;
if (edp_pipe_is_enabled(vgpu) &&
@@ -187,8 +187,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
for_each_pipe(dev_priv, pipe) {
- vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
- ~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
+ vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &=
+ ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
@@ -248,8 +248,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
* TRANSCODER_A can be enabled. PORT_x depends on the input of
* setup_virtual_dp_monitor.
*/
- vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
- vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
+ vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
+ vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
/*
* Golden M/N are calculated based on:
@@ -506,7 +506,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
}
- vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
+ vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
}
static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
@@ -584,7 +584,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
* @turnon: Turn ON/OFF vblank_timer
*
* This function is used to turn on/off or update the per-vGPU vblank_timer
- * when PIPECONF is enabled or disabled. vblank_timer period is also updated
+ * when TRANSCONF is enabled or disabled. vblank_timer period is also updated
* if guest changed the refresh rate.
*
*/
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index eed15fbc7069..3c8e0d198c4f 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -697,12 +697,12 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
write_vreg(vgpu, offset, p_data, bytes);
data = vgpu_vreg(vgpu, offset);
- if (data & PIPECONF_ENABLE) {
- vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
+ if (data & TRANSCONF_ENABLE) {
+ vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
vgpu_update_refresh_rate(vgpu);
vgpu_update_vblank_emulation(vgpu, true);
} else {
- vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
+ vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
vgpu_update_vblank_emulation(vgpu, false);
}
return 0;
@@ -2262,10 +2262,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
/* display */
- MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
- MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write);
+ MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write);
MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
reg50080_mmio_write);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 28b1226688b8..04de4d0671b7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3444,61 +3444,61 @@
#define _PIPEADSL 0x70000
#define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
#define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
-#define _PIPEACONF 0x70008
-#define PIPECONF_ENABLE REG_BIT(31)
-#define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
-#define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
-#define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
-#define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
-#define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
-#define PIPECONF_PIPE_LOCKED REG_BIT(25)
-#define PIPECONF_FORCE_BORDER REG_BIT(25)
-#define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
-#define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
-#define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
-#define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
-#define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
-#define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
-#define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
-#define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
-#define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
-#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
-#define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
-#define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
-#define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
+#define _TRANSACONF 0x70008
+#define TRANSCONF_ENABLE REG_BIT(31)
+#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
+#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
+#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
+#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
+#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
+#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
+#define TRANSCONF_FORCE_BORDER REG_BIT(25)
+#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
+#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
+#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
+#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
+#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
+#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
+#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
+#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
+#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
+#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
+#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
/*
* ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
* DBL=power saving pixel doubling, PF-ID* requires panel fitter
*/
-#define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
-#define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
-#define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
-#define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
-#define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
-#define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
-#define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
-#define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
-#define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
-#define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
-#define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
-#define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
-#define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
-#define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
-#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
-#define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
-#define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
-#define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
-#define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
-#define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
-#define PIPECONF_DITHER_EN REG_BIT(4)
-#define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
-#define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
-#define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
-#define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
-#define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
+#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
+#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
+#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
+#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
+#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
+#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
+#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
+#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
+#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
+#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
+#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
+#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
+#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
+#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
+#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
+#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
+#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
+#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
+#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
+#define TRANSCONF_DITHER_EN REG_BIT(4)
+#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
+#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
+#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
+#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
+#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
#define _PIPEASTAT 0x70024
#define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
@@ -3567,7 +3567,7 @@
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
-#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
+#define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF)
#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
@@ -4207,7 +4207,7 @@
/* Pipe B */
#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
-#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
+#define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
#define _PIPEBFRAMEHIGH 0x71040
#define _PIPEBFRAMEPIXEL 0x71044
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index d649ff2bb780..2b3fe469b360 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -118,10 +118,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
MMIO_D(PIPEDSL(PIPE_B));
MMIO_D(PIPEDSL(PIPE_C));
MMIO_D(PIPEDSL(_PIPE_EDP));
- MMIO_D(PIPECONF(PIPE_A));
- MMIO_D(PIPECONF(PIPE_B));
- MMIO_D(PIPECONF(PIPE_C));
- MMIO_D(PIPECONF(_PIPE_EDP));
+ MMIO_D(TRANSCONF(TRANSCODER_A));
+ MMIO_D(TRANSCONF(TRANSCODER_B));
+ MMIO_D(TRANSCONF(TRANSCODER_C));
+ MMIO_D(TRANSCONF(TRANSCODER_EDP));
MMIO_D(PIPESTAT(PIPE_A));
MMIO_D(PIPESTAT(PIPE_B));
MMIO_D(PIPESTAT(PIPE_C));
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/
2023-02-13 22:52 ` [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/ Ville Syrjala
@ 2023-02-14 10:05 ` Jani Nikula
2023-02-14 10:32 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Jani Nikula @ 2023-02-14 10:05 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename PIPECONF to TRANSCONF to make it clear what it actually
> applies to.
>
> While the usual convention is to pick the earliers name I think
> in this case it's more clear to use the later name. Especially
> as even the register offset is in the wrong range (0x70000 vs.
> 0x60000) and thus makes it look like this is per-pipe.
>
> There is one place in gvt that's doing something with TRANSCONF
> while iterating with for_each_pipe(). So that might not be doing
> the right thing for TRANSCODER_EDP, dunno. Not knowing what it
> does I left it as is to avoid breakage.
I recently looked at _PIPE_EDP usage, and thought all of it looked a bit
suspect, but didn't bother to dig deeper. Maybe after this it could be
removed?
BR,
Jani.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 16 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 10 +-
> drivers/gpu/drm/i915/display/intel_display.c | 171 +++++++++---------
> .../i915/display/intel_display_power_well.c | 8 +-
> drivers/gpu/drm/i915/display/intel_drrs.c | 8 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 8 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 16 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 2 +-
> drivers/gpu/drm/i915/gvt/display.c | 16 +-
> drivers/gpu/drm/i915/gvt/handlers.c | 14 +-
> drivers/gpu/drm/i915/i915_reg.h | 106 +++++------
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 +-
> 12 files changed, 192 insertions(+), 191 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index e1fe59ca0892..07897d6f9c53 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -976,11 +976,11 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
>
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_rmw(dev_priv, PIPECONF(dsi_trans), 0, PIPECONF_ENABLE);
> + intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE);
>
> /* wait for transcoder to be enabled */
> - if (intel_de_wait_for_set(dev_priv, PIPECONF(dsi_trans),
> - PIPECONF_STATE_ENABLE, 10))
> + if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
> + TRANSCONF_STATE_ENABLE, 10))
> drm_err(&dev_priv->drm,
> "DSI transcoder not enabled\n");
> }
> @@ -1238,11 +1238,11 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
> dsi_trans = dsi_port_to_transcoder(port);
>
> /* disable transcoder */
> - intel_de_rmw(dev_priv, PIPECONF(dsi_trans), PIPECONF_ENABLE, 0);
> + intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0);
>
> /* wait for transcoder to be disabled */
> - if (intel_de_wait_for_clear(dev_priv, PIPECONF(dsi_trans),
> - PIPECONF_STATE_ENABLE, 50))
> + if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
> + TRANSCONF_STATE_ENABLE, 50))
> drm_err(&dev_priv->drm,
> "DSI trancoder not disabled\n");
> }
> @@ -1662,8 +1662,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> goto out;
> }
>
> - tmp = intel_de_read(dev_priv, PIPECONF(dsi_trans));
> - ret = tmp & PIPECONF_ENABLE;
> + tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));
> + ret = tmp & TRANSCONF_ENABLE;
> }
> out:
> intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 4b7f8cd416fe..ef0c7f5b0ad6 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -708,11 +708,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
>
> if (DISPLAY_VER(dev_priv) != 2) {
> - u32 pipeconf = intel_de_read(dev_priv, PIPECONF(pipe));
> + u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
>
> - intel_de_write(dev_priv, PIPECONF(pipe),
> - pipeconf | PIPECONF_FORCE_BORDER);
> - intel_de_posting_read(dev_priv, PIPECONF(pipe));
> + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
> + transconf | TRANSCONF_FORCE_BORDER);
> + intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> /* Wait for next Vblank to substitue
> * border color for Color info */
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
> @@ -721,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> connector_status_connected :
> connector_status_disconnected;
>
> - intel_de_write(dev_priv, PIPECONF(pipe), pipeconf);
> + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
> } else {
> bool restore_vblank = false;
> int count, detect;
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a93f3630e9f8..0aca842df8f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -396,8 +396,8 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
> enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
>
> /* Wait for the Pipe State to go off */
> - if (intel_de_wait_for_clear(dev_priv, PIPECONF(cpu_transcoder),
> - PIPECONF_STATE_ENABLE, 100))
> + if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
> + TRANSCONF_STATE_ENABLE, 100))
> drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
> } else {
> intel_wait_for_pipe_scanline_stopped(crtc);
> @@ -418,8 +418,8 @@ void assert_transcoder(struct drm_i915_private *dev_priv,
> power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
> if (wakeref) {
> - u32 val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
> - cur_state = !!(val & PIPECONF_ENABLE);
> + u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
> + cur_state = !!(val & TRANSCONF_ENABLE);
>
> intel_display_power_put(dev_priv, power_domain, wakeref);
> } else {
> @@ -531,15 +531,15 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
> intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
> 0, PIPE_ARB_USE_PROG_SLOTS);
>
> - reg = PIPECONF(cpu_transcoder);
> + reg = TRANSCONF(cpu_transcoder);
> val = intel_de_read(dev_priv, reg);
> - if (val & PIPECONF_ENABLE) {
> + if (val & TRANSCONF_ENABLE) {
> /* we keep both pipes enabled on 830 */
> drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
> return;
> }
>
> - intel_de_write(dev_priv, reg, val | PIPECONF_ENABLE);
> + intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
> intel_de_posting_read(dev_priv, reg);
>
> /*
> @@ -570,9 +570,9 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
> */
> assert_planes_disabled(crtc);
>
> - reg = PIPECONF(cpu_transcoder);
> + reg = TRANSCONF(cpu_transcoder);
> val = intel_de_read(dev_priv, reg);
> - if ((val & PIPECONF_ENABLE) == 0)
> + if ((val & TRANSCONF_ENABLE) == 0)
> return;
>
> /*
> @@ -580,11 +580,11 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
> * so best keep it disabled when not needed.
> */
> if (old_crtc_state->double_wide)
> - val &= ~PIPECONF_DOUBLE_WIDE;
> + val &= ~TRANSCONF_DOUBLE_WIDE;
>
> /* Don't disable pipe or pipe PLLs if needed */
> if (!IS_I830(dev_priv))
> - val &= ~PIPECONF_ENABLE;
> + val &= ~TRANSCONF_ENABLE;
>
> if (DISPLAY_VER(dev_priv) >= 14)
> intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
> @@ -594,7 +594,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
> FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
>
> intel_de_write(dev_priv, reg, val);
> - if ((val & PIPECONF_ENABLE) == 0)
> + if ((val & TRANSCONF_ENABLE) == 0)
> intel_wait_for_pipe_off(old_crtc_state);
> }
>
> @@ -2897,9 +2897,9 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
>
> if (DISPLAY_VER(dev_priv) >= 9 ||
> IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
> - return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK_HSW;
> + return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
> else
> - return intel_de_read(dev_priv, PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK;
> + return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
> }
>
> static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> @@ -2984,7 +2984,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - u32 pipeconf = 0;
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> + u32 val = 0;
>
> /*
> * - We keep both pipes enabled on 830
> @@ -2992,18 +2993,18 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> * - During fastset the pipe is already enabled and must remain so
> */
> if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
> - pipeconf |= PIPECONF_ENABLE;
> + val |= TRANSCONF_ENABLE;
>
> if (crtc_state->double_wide)
> - pipeconf |= PIPECONF_DOUBLE_WIDE;
> + val |= TRANSCONF_DOUBLE_WIDE;
>
> /* only g4x and later have fancy bpc/dither controls */
> if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) {
> /* Bspec claims that we can't use dithering for 30bpp pipes. */
> if (crtc_state->dither && crtc_state->pipe_bpp != 30)
> - pipeconf |= PIPECONF_DITHER_EN |
> - PIPECONF_DITHER_TYPE_SP;
> + val |= TRANSCONF_DITHER_EN |
> + TRANSCONF_DITHER_TYPE_SP;
>
> switch (crtc_state->pipe_bpp) {
> default:
> @@ -3011,13 +3012,13 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> MISSING_CASE(crtc_state->pipe_bpp);
> fallthrough;
> case 18:
> - pipeconf |= PIPECONF_BPC_6;
> + val |= TRANSCONF_BPC_6;
> break;
> case 24:
> - pipeconf |= PIPECONF_BPC_8;
> + val |= TRANSCONF_BPC_8;
> break;
> case 30:
> - pipeconf |= PIPECONF_BPC_10;
> + val |= TRANSCONF_BPC_10;
> break;
> }
> }
> @@ -3025,23 +3026,23 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> if (DISPLAY_VER(dev_priv) < 4 ||
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> - pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
> + val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
> else
> - pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
> + val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
> } else {
> - pipeconf |= PIPECONF_INTERLACE_PROGRESSIVE;
> + val |= TRANSCONF_INTERLACE_PROGRESSIVE;
> }
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> crtc_state->limited_color_range)
> - pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
> + val |= TRANSCONF_COLOR_RANGE_SELECT;
>
> - pipeconf |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> + val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
>
> - pipeconf |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
> + val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
>
> - intel_de_write(dev_priv, PIPECONF(crtc->pipe), pipeconf);
> - intel_de_posting_read(dev_priv, PIPECONF(crtc->pipe));
> + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> + intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> }
>
> static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
> @@ -3200,20 +3201,20 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
>
> ret = false;
>
> - tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
> - if (!(tmp & PIPECONF_ENABLE))
> + tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
> + if (!(tmp & TRANSCONF_ENABLE))
> goto out;
>
> if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
> IS_CHERRYVIEW(dev_priv)) {
> - switch (tmp & PIPECONF_BPC_MASK) {
> - case PIPECONF_BPC_6:
> + switch (tmp & TRANSCONF_BPC_MASK) {
> + case TRANSCONF_BPC_6:
> pipe_config->pipe_bpp = 18;
> break;
> - case PIPECONF_BPC_8:
> + case TRANSCONF_BPC_8:
> pipe_config->pipe_bpp = 24;
> break;
> - case PIPECONF_BPC_10:
> + case TRANSCONF_BPC_10:
> pipe_config->pipe_bpp = 30;
> break;
> default:
> @@ -3223,12 +3224,12 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> }
>
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> - (tmp & PIPECONF_COLOR_RANGE_SELECT))
> + (tmp & TRANSCONF_COLOR_RANGE_SELECT))
> pipe_config->limited_color_range = true;
>
> - pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_I9XX, tmp);
> + pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
>
> - pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
> + pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
>
> if (IS_CHERRYVIEW(dev_priv))
> pipe_config->cgm_mode = intel_de_read(dev_priv,
> @@ -3238,7 +3239,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
> intel_color_get_config(pipe_config);
>
> if (DISPLAY_VER(dev_priv) < 4)
> - pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
> + pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
>
> intel_get_transcoder_timings(crtc, pipe_config);
> intel_get_pipe_src_size(crtc, pipe_config);
> @@ -3308,7 +3309,7 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - enum pipe pipe = crtc->pipe;
> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> u32 val = 0;
>
> /*
> @@ -3316,7 +3317,7 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
> * - During fastset the pipe is already enabled and must remain so
> */
> if (!intel_crtc_needs_modeset(crtc_state))
> - val |= PIPECONF_ENABLE;
> + val |= TRANSCONF_ENABLE;
>
> switch (crtc_state->pipe_bpp) {
> default:
> @@ -3324,26 +3325,26 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
> MISSING_CASE(crtc_state->pipe_bpp);
> fallthrough;
> case 18:
> - val |= PIPECONF_BPC_6;
> + val |= TRANSCONF_BPC_6;
> break;
> case 24:
> - val |= PIPECONF_BPC_8;
> + val |= TRANSCONF_BPC_8;
> break;
> case 30:
> - val |= PIPECONF_BPC_10;
> + val |= TRANSCONF_BPC_10;
> break;
> case 36:
> - val |= PIPECONF_BPC_12;
> + val |= TRANSCONF_BPC_12;
> break;
> }
>
> if (crtc_state->dither)
> - val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
> + val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
>
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> - val |= PIPECONF_INTERLACE_IF_ID_ILK;
> + val |= TRANSCONF_INTERLACE_IF_ID_ILK;
> else
> - val |= PIPECONF_INTERLACE_PF_PD_ILK;
> + val |= TRANSCONF_INTERLACE_PF_PD_ILK;
>
> /*
> * This would end up with an odd purple hue over
> @@ -3354,18 +3355,18 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
>
> if (crtc_state->limited_color_range &&
> !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> - val |= PIPECONF_COLOR_RANGE_SELECT;
> + val |= TRANSCONF_COLOR_RANGE_SELECT;
>
> if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> - val |= PIPECONF_OUTPUT_COLORSPACE_YUV709;
> + val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
>
> - val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
> + val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
>
> - val |= PIPECONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
> - val |= PIPECONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
> + val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
> + val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
>
> - intel_de_write(dev_priv, PIPECONF(pipe), val);
> - intel_de_posting_read(dev_priv, PIPECONF(pipe));
> + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> + intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> }
>
> static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
> @@ -3380,22 +3381,22 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
> * - During fastset the pipe is already enabled and must remain so
> */
> if (!intel_crtc_needs_modeset(crtc_state))
> - val |= PIPECONF_ENABLE;
> + val |= TRANSCONF_ENABLE;
>
> if (IS_HASWELL(dev_priv) && crtc_state->dither)
> - val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
> + val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
>
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> - val |= PIPECONF_INTERLACE_IF_ID_ILK;
> + val |= TRANSCONF_INTERLACE_IF_ID_ILK;
> else
> - val |= PIPECONF_INTERLACE_PF_PD_ILK;
> + val |= TRANSCONF_INTERLACE_PF_PD_ILK;
>
> if (IS_HASWELL(dev_priv) &&
> crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> - val |= PIPECONF_OUTPUT_COLORSPACE_YUV_HSW;
> + val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
>
> - intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
> - intel_de_posting_read(dev_priv, PIPECONF(cpu_transcoder));
> + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> + intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
> }
>
> static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state)
> @@ -3620,33 +3621,33 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> pipe_config->shared_dpll = NULL;
>
> ret = false;
> - tmp = intel_de_read(dev_priv, PIPECONF(crtc->pipe));
> - if (!(tmp & PIPECONF_ENABLE))
> + tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
> + if (!(tmp & TRANSCONF_ENABLE))
> goto out;
>
> - switch (tmp & PIPECONF_BPC_MASK) {
> - case PIPECONF_BPC_6:
> + switch (tmp & TRANSCONF_BPC_MASK) {
> + case TRANSCONF_BPC_6:
> pipe_config->pipe_bpp = 18;
> break;
> - case PIPECONF_BPC_8:
> + case TRANSCONF_BPC_8:
> pipe_config->pipe_bpp = 24;
> break;
> - case PIPECONF_BPC_10:
> + case TRANSCONF_BPC_10:
> pipe_config->pipe_bpp = 30;
> break;
> - case PIPECONF_BPC_12:
> + case TRANSCONF_BPC_12:
> pipe_config->pipe_bpp = 36;
> break;
> default:
> break;
> }
>
> - if (tmp & PIPECONF_COLOR_RANGE_SELECT)
> + if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
> pipe_config->limited_color_range = true;
>
> - switch (tmp & PIPECONF_OUTPUT_COLORSPACE_MASK) {
> - case PIPECONF_OUTPUT_COLORSPACE_YUV601:
> - case PIPECONF_OUTPUT_COLORSPACE_YUV709:
> + switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
> + case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
> + case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
> break;
> default:
> @@ -3654,11 +3655,11 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc,
> break;
> }
>
> - pipe_config->gamma_mode = REG_FIELD_GET(PIPECONF_GAMMA_MODE_MASK_ILK, tmp);
> + pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
>
> - pipe_config->framestart_delay = REG_FIELD_GET(PIPECONF_FRAME_START_DELAY_MASK, tmp) + 1;
> + pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
>
> - pipe_config->msa_timing_delay = REG_FIELD_GET(PIPECONF_MSA_TIMING_DELAY_MASK, tmp);
> + pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
>
> pipe_config->csc_mode = intel_de_read(dev_priv,
> PIPE_CSC_MODE(crtc->pipe));
> @@ -3935,9 +3936,9 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> pipe_config->pch_pfit.force_thru = true;
> }
>
> - tmp = intel_de_read(dev_priv, PIPECONF(pipe_config->cpu_transcoder));
> + tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
>
> - return tmp & PIPECONF_ENABLE;
> + return tmp & TRANSCONF_ENABLE;
> }
>
> static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> @@ -4041,9 +4042,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
>
> if (IS_HASWELL(dev_priv)) {
> u32 tmp = intel_de_read(dev_priv,
> - PIPECONF(pipe_config->cpu_transcoder));
> + TRANSCONF(pipe_config->cpu_transcoder));
>
> - if (tmp & PIPECONF_OUTPUT_COLORSPACE_YUV_HSW)
> + if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
> else
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> @@ -8855,8 +8856,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> udelay(150); /* wait for warmup */
> }
>
> - intel_de_write(dev_priv, PIPECONF(pipe), PIPECONF_ENABLE);
> - intel_de_posting_read(dev_priv, PIPECONF(pipe));
> + intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
> + intel_de_posting_read(dev_priv, TRANSCONF(pipe));
>
> intel_wait_for_pipe_scanline_moving(crtc);
> }
> @@ -8879,8 +8880,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> drm_WARN_ON(&dev_priv->drm,
> intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
>
> - intel_de_write(dev_priv, PIPECONF(pipe), 0);
> - intel_de_posting_read(dev_priv, PIPECONF(pipe));
> + intel_de_write(dev_priv, TRANSCONF(pipe), 0);
> + intel_de_posting_read(dev_priv, TRANSCONF(pipe));
>
> intel_wait_for_pipe_scanline_stopped(crtc);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8710dd41ffd4..b34851e42614 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1033,9 +1033,9 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
> static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
> + if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0)
> i830_enable_pipe(dev_priv, PIPE_A);
> - if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
> + if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0)
> i830_enable_pipe(dev_priv, PIPE_B);
> }
>
> @@ -1049,8 +1049,8 @@ static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
> static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
> - intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
> + return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE &&
> + intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
> }
>
> static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c
> index 29c6421cd666..fe4c531a2574 100644
> --- a/drivers/gpu/drm/i915/display/intel_drrs.c
> +++ b/drivers/gpu/drm/i915/display/intel_drrs.c
> @@ -71,18 +71,18 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc,
> u32 val, bit;
>
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> - bit = PIPECONF_REFRESH_RATE_ALT_VLV;
> + bit = TRANSCONF_REFRESH_RATE_ALT_VLV;
> else
> - bit = PIPECONF_REFRESH_RATE_ALT_ILK;
> + bit = TRANSCONF_REFRESH_RATE_ALT_ILK;
>
> - val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
> + val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
>
> if (refresh_rate == DRRS_REFRESH_RATE_LOW)
> val |= bit;
> else
> val &= ~bit;
>
> - intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val);
> + intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index f62d9a931349..091d4d36d9de 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -902,7 +902,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state)
> temp = intel_de_read(dev_priv, reg);
> temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
> temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
> - temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
> + temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
> intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE);
>
> intel_de_posting_read(dev_priv, reg);
> @@ -958,7 +958,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> reg = FDI_RX_CTL(pipe);
> temp = intel_de_read(dev_priv, reg);
> temp &= ~(0x7 << 16);
> - temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
> + temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
> intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE);
>
> intel_de_posting_read(dev_priv, reg);
> @@ -982,9 +982,9 @@ void ilk_fdi_disable(struct intel_crtc *crtc)
> temp &= ~FDI_LINK_TRAIN_NONE;
> temp |= FDI_LINK_TRAIN_PATTERN_1;
> }
> - /* BPC in FDI rx is consistent with that in PIPECONF */
> + /* BPC in FDI rx is consistent with that in TRANSCONF */
> temp &= ~(0x07 << 16);
> - temp |= (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
> + temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11;
> intel_de_write(dev_priv, reg, temp);
>
> intel_de_posting_read(dev_priv, reg);
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index e55bc4763278..c1d336f39770 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -267,7 +267,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
>
> reg = PCH_TRANSCONF(pipe);
> val = intel_de_read(dev_priv, reg);
> - pipeconf_val = intel_de_read(dev_priv, PIPECONF(pipe));
> + pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe));
>
> if (HAS_PCH_IBX(dev_priv)) {
> /* Configure frame start delay to match the CPU */
> @@ -279,15 +279,15 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> * that in pipeconf reg. For HDMI we must use 8bpc
> * here for both 8bpc and 12bpc.
> */
> - val &= ~PIPECONF_BPC_MASK;
> + val &= ~TRANSCONF_BPC_MASK;
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
> - val |= PIPECONF_BPC_8;
> + val |= TRANSCONF_BPC_8;
> else
> - val |= pipeconf_val & PIPECONF_BPC_MASK;
> + val |= pipeconf_val & TRANSCONF_BPC_MASK;
> }
>
> val &= ~TRANS_INTERLACE_MASK;
> - if ((pipeconf_val & PIPECONF_INTERLACE_MASK_ILK) == PIPECONF_INTERLACE_IF_ID_ILK) {
> + if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_ILK) == TRANSCONF_INTERLACE_IF_ID_ILK) {
> if (HAS_PCH_IBX(dev_priv) &&
> intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
> val |= TRANS_INTERLACE_LEGACY_VSYNC_IBX;
> @@ -415,7 +415,7 @@ void ilk_pch_enable(struct intel_atomic_state *state,
> intel_crtc_has_dp_encoder(crtc_state)) {
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> - u32 bpc = (intel_de_read(dev_priv, PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
> + u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5;
> i915_reg_t reg = TRANS_DP_CTL(pipe);
> enum port port;
>
> @@ -566,9 +566,9 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state)
> intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val);
>
> val = TRANS_ENABLE;
> - pipeconf_val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder));
> + pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
>
> - if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == PIPECONF_INTERLACE_IF_ID_ILK)
> + if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK)
> val |= TRANS_INTERLACE_INTERLACED;
> else
> val |= TRANS_INTERLACE_PROGRESSIVE;
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index 2c945a949ad2..8d2e6e151ba0 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -1000,7 +1000,7 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
> */
> if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
> port == PORT_C)
> - enabled = intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
> + enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE;
>
> /* Try command mode if video mode not enabled */
> if (!enabled) {
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 4d898b14de93..e0c5dfb788eb 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -63,7 +63,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
> {
> struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
>
> - if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
> + if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE))
> return 0;
>
> if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
> @@ -79,7 +79,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
> pipe < PIPE_A || pipe >= I915_MAX_PIPES))
> return -EINVAL;
>
> - if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
> + if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE)
> return 1;
>
> if (edp_pipe_is_enabled(vgpu) &&
> @@ -187,8 +187,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> GEN8_DE_PORT_HOTPLUG(HPD_PORT_C));
>
> for_each_pipe(dev_priv, pipe) {
> - vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
> - ~(PIPECONF_ENABLE | PIPECONF_STATE_ENABLE);
> + vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &=
> + ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE);
> vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
> vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
> vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
> @@ -248,8 +248,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> * TRANSCODER_A can be enabled. PORT_x depends on the input of
> * setup_virtual_dp_monitor.
> */
> - vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
> - vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_STATE_ENABLE;
> + vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
> + vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
>
> /*
> * Golden M/N are calculated based on:
> @@ -506,7 +506,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
> vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
> }
>
> - vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
> + vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
> }
>
> static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
> @@ -584,7 +584,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
> * @turnon: Turn ON/OFF vblank_timer
> *
> * This function is used to turn on/off or update the per-vGPU vblank_timer
> - * when PIPECONF is enabled or disabled. vblank_timer period is also updated
> + * when TRANSCONF is enabled or disabled. vblank_timer period is also updated
> * if guest changed the refresh rate.
> *
> */
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index eed15fbc7069..3c8e0d198c4f 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -697,12 +697,12 @@ static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
> write_vreg(vgpu, offset, p_data, bytes);
> data = vgpu_vreg(vgpu, offset);
>
> - if (data & PIPECONF_ENABLE) {
> - vgpu_vreg(vgpu, offset) |= PIPECONF_STATE_ENABLE;
> + if (data & TRANSCONF_ENABLE) {
> + vgpu_vreg(vgpu, offset) |= TRANSCONF_STATE_ENABLE;
> vgpu_update_refresh_rate(vgpu);
> vgpu_update_vblank_emulation(vgpu, true);
> } else {
> - vgpu_vreg(vgpu, offset) &= ~PIPECONF_STATE_ENABLE;
> + vgpu_vreg(vgpu, offset) &= ~TRANSCONF_STATE_ENABLE;
> vgpu_update_vblank_emulation(vgpu, false);
> }
> return 0;
> @@ -2262,10 +2262,10 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
>
> /* display */
> - MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
> - MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write);
> + MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write);
> MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
> MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL,
> reg50080_mmio_write);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 28b1226688b8..04de4d0671b7 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3444,61 +3444,61 @@
> #define _PIPEADSL 0x70000
> #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */
> #define PIPEDSL_LINE_MASK REG_GENMASK(19, 0)
> -#define _PIPEACONF 0x70008
> -#define PIPECONF_ENABLE REG_BIT(31)
> -#define PIPECONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
> -#define PIPECONF_STATE_ENABLE REG_BIT(30) /* i965+ */
> -#define PIPECONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
> -#define PIPECONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
> -#define PIPECONF_FRAME_START_DELAY(x) REG_FIELD_PREP(PIPECONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
> -#define PIPECONF_PIPE_LOCKED REG_BIT(25)
> -#define PIPECONF_FORCE_BORDER REG_BIT(25)
> -#define PIPECONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
> -#define PIPECONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
> -#define PIPECONF_GAMMA_MODE_8BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 0)
> -#define PIPECONF_GAMMA_MODE_10BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK, 1)
> -#define PIPECONF_GAMMA_MODE_12BIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
> -#define PIPECONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
> -#define PIPECONF_GAMMA_MODE(x) REG_FIELD_PREP(PIPECONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
> -#define PIPECONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
> -#define PIPECONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 0)
> -#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 4) /* gen4 only */
> -#define PIPECONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 5) /* gen4 only */
> -#define PIPECONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 6)
> -#define PIPECONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(PIPECONF_INTERLACE_MASK, 7) /* gen3 only */
> +#define _TRANSACONF 0x70008
> +#define TRANSCONF_ENABLE REG_BIT(31)
> +#define TRANSCONF_DOUBLE_WIDE REG_BIT(30) /* pre-i965 */
> +#define TRANSCONF_STATE_ENABLE REG_BIT(30) /* i965+ */
> +#define TRANSCONF_DSI_PLL_LOCKED REG_BIT(29) /* vlv & pipe A only */
> +#define TRANSCONF_FRAME_START_DELAY_MASK REG_GENMASK(28, 27) /* pre-hsw */
> +#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
> +#define TRANSCONF_PIPE_LOCKED REG_BIT(25)
> +#define TRANSCONF_FORCE_BORDER REG_BIT(25)
> +#define TRANSCONF_GAMMA_MODE_MASK_I9XX REG_BIT(24) /* gmch */
> +#define TRANSCONF_GAMMA_MODE_MASK_ILK REG_GENMASK(25, 24) /* ilk-ivb */
> +#define TRANSCONF_GAMMA_MODE_8BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 0)
> +#define TRANSCONF_GAMMA_MODE_10BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK, 1)
> +#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
> +#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
> +#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
> +#define TRANSCONF_INTERLACE_MASK REG_GENMASK(23, 21) /* gen3+ */
> +#define TRANSCONF_INTERLACE_PROGRESSIVE REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 0)
> +#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
> +#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
> +#define TRANSCONF_INTERLACE_W_FIELD_INDICATION REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 6)
> +#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
> /*
> * ilk+: PF/D=progressive fetch/display, IF/D=interlaced fetch/display,
> * DBL=power saving pixel doubling, PF-ID* requires panel fitter
> */
> -#define PIPECONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
> -#define PIPECONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
> -#define PIPECONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 0)
> -#define PIPECONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 1)
> -#define PIPECONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 3)
> -#define PIPECONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
> -#define PIPECONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(PIPECONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
> -#define PIPECONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
> -#define PIPECONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
> -#define PIPECONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(PIPECONF_MSA_TIMING_DELAY_MASK, (x))
> -#define PIPECONF_CXSR_DOWNCLOCK REG_BIT(16)
> -#define PIPECONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
> -#define PIPECONF_COLOR_RANGE_SELECT REG_BIT(13)
> -#define PIPECONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
> -#define PIPECONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
> -#define PIPECONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
> -#define PIPECONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(PIPECONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
> -#define PIPECONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
> -#define PIPECONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
> -#define PIPECONF_BPC_8 REG_FIELD_PREP(PIPECONF_BPC_MASK, 0)
> -#define PIPECONF_BPC_10 REG_FIELD_PREP(PIPECONF_BPC_MASK, 1)
> -#define PIPECONF_BPC_6 REG_FIELD_PREP(PIPECONF_BPC_MASK, 2)
> -#define PIPECONF_BPC_12 REG_FIELD_PREP(PIPECONF_BPC_MASK, 3)
> -#define PIPECONF_DITHER_EN REG_BIT(4)
> -#define PIPECONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
> -#define PIPECONF_DITHER_TYPE_SP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 0)
> -#define PIPECONF_DITHER_TYPE_ST1 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 1)
> -#define PIPECONF_DITHER_TYPE_ST2 REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 2)
> -#define PIPECONF_DITHER_TYPE_TEMP REG_FIELD_PREP(PIPECONF_DITHER_TYPE_MASK, 3)
> +#define TRANSCONF_INTERLACE_MASK_ILK REG_GENMASK(23, 21) /* ilk+ */
> +#define TRANSCONF_INTERLACE_MASK_HSW REG_GENMASK(22, 21) /* hsw+ */
> +#define TRANSCONF_INTERLACE_PF_PD_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 0)
> +#define TRANSCONF_INTERLACE_PF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 1)
> +#define TRANSCONF_INTERLACE_IF_ID_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 3)
> +#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
> +#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
> +#define TRANSCONF_REFRESH_RATE_ALT_ILK REG_BIT(20)
> +#define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */
> +#define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x))
> +#define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16)
> +#define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14)
> +#define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13)
> +#define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
> +#define TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW REG_BIT(11) /* hsw only */
> +#define TRANSCONF_BPC_MASK REG_GENMASK(7, 5) /* ctg-ivb */
> +#define TRANSCONF_BPC_8 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 0)
> +#define TRANSCONF_BPC_10 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 1)
> +#define TRANSCONF_BPC_6 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 2)
> +#define TRANSCONF_BPC_12 REG_FIELD_PREP(TRANSCONF_BPC_MASK, 3)
> +#define TRANSCONF_DITHER_EN REG_BIT(4)
> +#define TRANSCONF_DITHER_TYPE_MASK REG_GENMASK(3, 2)
> +#define TRANSCONF_DITHER_TYPE_SP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 0)
> +#define TRANSCONF_DITHER_TYPE_ST1 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 1)
> +#define TRANSCONF_DITHER_TYPE_ST2 REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 2)
> +#define TRANSCONF_DITHER_TYPE_TEMP REG_FIELD_PREP(TRANSCONF_DITHER_TYPE_MASK, 3)
> #define _PIPEASTAT 0x70024
> #define PIPE_FIFO_UNDERRUN_STATUS (1UL << 31)
> #define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL << 30)
> @@ -3567,7 +3567,7 @@
> #define PIPE_DSI0_OFFSET 0x7b000
> #define PIPE_DSI1_OFFSET 0x7b800
>
> -#define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF)
> +#define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF)
> #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL)
> #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
> #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL)
> @@ -4207,7 +4207,7 @@
>
> /* Pipe B */
> #define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000)
> -#define _PIPEBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
> +#define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008)
> #define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024)
> #define _PIPEBFRAMEHIGH 0x71040
> #define _PIPEBFRAMEPIXEL 0x71044
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index d649ff2bb780..2b3fe469b360 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -118,10 +118,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter)
> MMIO_D(PIPEDSL(PIPE_B));
> MMIO_D(PIPEDSL(PIPE_C));
> MMIO_D(PIPEDSL(_PIPE_EDP));
> - MMIO_D(PIPECONF(PIPE_A));
> - MMIO_D(PIPECONF(PIPE_B));
> - MMIO_D(PIPECONF(PIPE_C));
> - MMIO_D(PIPECONF(_PIPE_EDP));
> + MMIO_D(TRANSCONF(TRANSCODER_A));
> + MMIO_D(TRANSCONF(TRANSCODER_B));
> + MMIO_D(TRANSCONF(TRANSCODER_C));
> + MMIO_D(TRANSCONF(TRANSCODER_EDP));
> MMIO_D(PIPESTAT(PIPE_A));
> MMIO_D(PIPESTAT(PIPE_B));
> MMIO_D(PIPESTAT(PIPE_C));
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/
2023-02-14 10:05 ` Jani Nikula
@ 2023-02-14 10:32 ` Ville Syrjälä
2023-02-14 10:52 ` Jani Nikula
0 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjälä @ 2023-02-14 10:32 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 14, 2023 at 12:05:33PM +0200, Jani Nikula wrote:
> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Rename PIPECONF to TRANSCONF to make it clear what it actually
> > applies to.
> >
> > While the usual convention is to pick the earliers name I think
> > in this case it's more clear to use the later name. Especially
> > as even the register offset is in the wrong range (0x70000 vs.
> > 0x60000) and thus makes it look like this is per-pipe.
> >
> > There is one place in gvt that's doing something with TRANSCONF
> > while iterating with for_each_pipe(). So that might not be doing
> > the right thing for TRANSCODER_EDP, dunno. Not knowing what it
> > does I left it as is to avoid breakage.
>
> I recently looked at _PIPE_EDP usage, and thought all of it looked a bit
> suspect, but didn't bother to dig deeper. Maybe after this it could be
> removed?
I think it needs to stay due to the pipe_offsets[] stuff
and hw making a mess of pipe vs. transcoder registers.
But no one should really use it anywhere else.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/
2023-02-14 10:32 ` Ville Syrjälä
@ 2023-02-14 10:52 ` Jani Nikula
2023-02-14 10:59 ` Ville Syrjälä
0 siblings, 1 reply; 27+ messages in thread
From: Jani Nikula @ 2023-02-14 10:52 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Tue, 14 Feb 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Tue, Feb 14, 2023 at 12:05:33PM +0200, Jani Nikula wrote:
>> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> >
>> > Rename PIPECONF to TRANSCONF to make it clear what it actually
>> > applies to.
>> >
>> > While the usual convention is to pick the earliers name I think
>> > in this case it's more clear to use the later name. Especially
>> > as even the register offset is in the wrong range (0x70000 vs.
>> > 0x60000) and thus makes it look like this is per-pipe.
>> >
>> > There is one place in gvt that's doing something with TRANSCONF
>> > while iterating with for_each_pipe(). So that might not be doing
>> > the right thing for TRANSCODER_EDP, dunno. Not knowing what it
>> > does I left it as is to avoid breakage.
>>
>> I recently looked at _PIPE_EDP usage, and thought all of it looked a bit
>> suspect, but didn't bother to dig deeper. Maybe after this it could be
>> removed?
>
> I think it needs to stay due to the pipe_offsets[] stuff
> and hw making a mess of pipe vs. transcoder registers.
> But no one should really use it anywhere else.
I wonder how many underscores more we need to add to keep it that
way. :p
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/
2023-02-14 10:52 ` Jani Nikula
@ 2023-02-14 10:59 ` Ville Syrjälä
0 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2023-02-14 10:59 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 14, 2023 at 12:52:46PM +0200, Jani Nikula wrote:
> On Tue, 14 Feb 2023, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> > On Tue, Feb 14, 2023 at 12:05:33PM +0200, Jani Nikula wrote:
> >> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> >> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >> >
> >> > Rename PIPECONF to TRANSCONF to make it clear what it actually
> >> > applies to.
> >> >
> >> > While the usual convention is to pick the earliers name I think
> >> > in this case it's more clear to use the later name. Especially
> >> > as even the register offset is in the wrong range (0x70000 vs.
> >> > 0x60000) and thus makes it look like this is per-pipe.
> >> >
> >> > There is one place in gvt that's doing something with TRANSCONF
> >> > while iterating with for_each_pipe(). So that might not be doing
> >> > the right thing for TRANSCODER_EDP, dunno. Not knowing what it
> >> > does I left it as is to avoid breakage.
> >>
> >> I recently looked at _PIPE_EDP usage, and thought all of it looked a bit
> >> suspect, but didn't bother to dig deeper. Maybe after this it could be
> >> removed?
> >
> > I think it needs to stay due to the pipe_offsets[] stuff
> > and hw making a mess of pipe vs. transcoder registers.
> > But no one should really use it anywhere else.
>
> I wonder how many underscores more we need to add to keep it that
> way. :p
People are probably accustomed to one or two. So maybe three?
Could also try adding a comment, but dunno if it would any
more effective.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 05/12] drm/i915: Dump blanking start/end
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (3 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 04/12] drm/i915: s/PIPECONF/TRANSCONF/ Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define the "unmodified vblank" interrupt bit Ville Syrjala
` (9 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With the delayed vblank we need to start knowing where
the blanking periods start. So let's start dumping
out also the blanking start/end timings.
And while at it let's try to make that huge list of
numbers somewhat legible by indicating what each value
means. Also drop the 'type' since that doesn't really
mean anything for the crtc_ timings.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_crtc_state_dump.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
index 2422d6ef5777..766633566fd6 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c
@@ -14,14 +14,16 @@
static void intel_dump_crtc_timings(struct drm_i915_private *i915,
const struct drm_display_mode *mode)
{
- drm_dbg_kms(&i915->drm, "crtc timings: %d %d %d %d %d %d %d %d %d, "
- "type: 0x%x flags: 0x%x\n",
+ drm_dbg_kms(&i915->drm, "crtc timings: clock=%d, "
+ "hd=%d hb=%d-%d hs=%d-%d ht=%d, "
+ "vd=%d vb=%d-%d vs=%d-%d vt=%d, "
+ "flags=0x%x\n",
mode->crtc_clock,
- mode->crtc_hdisplay, mode->crtc_hsync_start,
- mode->crtc_hsync_end, mode->crtc_htotal,
- mode->crtc_vdisplay, mode->crtc_vsync_start,
- mode->crtc_vsync_end, mode->crtc_vtotal,
- mode->type, mode->flags);
+ mode->crtc_hdisplay, mode->crtc_hblank_start, mode->crtc_hblank_end,
+ mode->crtc_hsync_start, mode->crtc_hsync_end, mode->crtc_htotal,
+ mode->crtc_vdisplay, mode->crtc_vblank_start, mode->crtc_vblank_end,
+ mode->crtc_vsync_start, mode->crtc_vsync_end, mode->crtc_vtotal,
+ mode->flags);
}
static void
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 06/12] drm/i915: Define the "unmodified vblank" interrupt bit
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (4 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 05/12] drm/i915: Dump blanking start/end Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 07/12] drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY Ville Syrjala
` (8 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On TGL+ the normal "start of vblank" interrupt is the pipe's
(potentially delayed) version. Add the new bit for the
transcoder's "unmodified" vblank so I don't have to dig it
out from bspec every time.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 04de4d0671b7..23886356af35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5384,6 +5384,7 @@
#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
#define XELPD_PIPE_SOFT_UNDERRUN (1 << 22)
#define XELPD_PIPE_HARD_UNDERRUN (1 << 21)
+#define GEN12_PIPE_VBLANK_UNMOD (1 << 19)
#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 07/12] drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (5 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 06/12] drm/i915: Define the "unmodified vblank" interrupt bit Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add local adjusted_mode variable Ville Syrjala
` (7 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The PSR code has no business mucking around with the
vblank delay. Currently nothing that depends on knowing
the exact vblank start scanline (eg. vblank evasion)
is aware of this and so will not work correctly.
The w/a seems to be for pre-production hw only, so let's
just nuke it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 13 -------------
1 file changed, 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a021f59f0ac7..cb02f572e1d8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1179,13 +1179,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0,
ADLP_1_BASED_X_GRANULARITY);
- /* Wa_16011168373:adl-p */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv,
- TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
- TRANS_SET_CONTEXT_LATENCY_MASK,
- TRANS_SET_CONTEXT_LATENCY_VALUE(1));
-
/* Wa_16012604467:adlp,mtl[a0,b0] */
if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
@@ -1350,12 +1343,6 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
wa_16013835468_bit_get(intel_dp), 0);
if (intel_dp->psr.psr2_enabled) {
- /* Wa_16011168373:adl-p */
- if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
- intel_de_rmw(dev_priv,
- TRANS_SET_CONTEXT_LATENCY(intel_dp->psr.transcoder),
- TRANS_SET_CONTEXT_LATENCY_MASK, 0);
-
/* Wa_16012604467:adlp,mtl[a0,b0] */
if (IS_MTL_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0))
intel_de_rmw(dev_priv,
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 08/12] drm/i915: Add local adjusted_mode variable
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (6 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 07/12] drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-13 22:52 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks Ville Syrjala
` (6 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Clean up the eyesore in intel_get_transcoder_timings() a
bit by adding a local 'adjusted_mode' variable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 35 +++++++++-----------
1 file changed, 16 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0aca842df8f7..ac021ca88e3c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2908,42 +2908,39 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
u32 tmp;
tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
- pipe_config->hw.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
- pipe_config->hw.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_hdisplay = (tmp & 0xffff) + 1;
+ adjusted_mode->crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
- pipe_config->hw.adjusted_mode.crtc_hblank_start =
- (tmp & 0xffff) + 1;
- pipe_config->hw.adjusted_mode.crtc_hblank_end =
- ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_hblank_start = (tmp & 0xffff) + 1;
+ adjusted_mode->crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
}
tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
- pipe_config->hw.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
- pipe_config->hw.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_hsync_start = (tmp & 0xffff) + 1;
+ adjusted_mode->crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
- pipe_config->hw.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
- pipe_config->hw.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_vdisplay = (tmp & 0xffff) + 1;
+ adjusted_mode->crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
- pipe_config->hw.adjusted_mode.crtc_vblank_start =
- (tmp & 0xffff) + 1;
- pipe_config->hw.adjusted_mode.crtc_vblank_end =
- ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_vblank_start = (tmp & 0xffff) + 1;
+ adjusted_mode->crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
}
tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
- pipe_config->hw.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
- pipe_config->hw.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_vsync_start = (tmp & 0xffff) + 1;
+ adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
if (intel_pipe_is_interlaced(pipe_config)) {
- pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
- pipe_config->hw.adjusted_mode.crtc_vtotal += 1;
- pipe_config->hw.adjusted_mode.crtc_vblank_end += 1;
+ adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
+ adjusted_mode->crtc_vtotal += 1;
+ adjusted_mode->crtc_vblank_end += 1;
}
}
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (7 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 08/12] drm/i915: Add local adjusted_mode variable Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-14 10:32 ` Jani Nikula
2023-02-13 22:52 ` [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+ Ville Syrjala
` (5 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Define the contents of the transcoder timing registers using
REG_GENMASK() & co. For ease of maintenance let's just define
the bitmasks with the full 16bit width (also used by the
current hand rolled stuff) even though not all bits are actually
used. None of the unsued bits have ever contained anything.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 10 +--
drivers/gpu/drm/i915/display/intel_crt.c | 13 ++--
drivers/gpu/drm/i915/display/intel_display.c | 64 ++++++++++++--------
drivers/gpu/drm/i915/i915_reg.h | 24 ++++++++
4 files changed, 75 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 07897d6f9c53..def3aff4d717 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -888,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
- (hactive - 1) | ((htotal - 1) << 16));
+ HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
}
/* TRANS_HSYNC register to be programmed only for video mode */
@@ -911,7 +911,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
- (hsync_start - 1) | ((hsync_end - 1) << 16));
+ HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
}
}
@@ -925,7 +925,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* For interlace mode: program required pixel minus 2
*/
intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
- (vactive - 1) | ((vtotal - 1) << 16));
+ VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
}
if (vsync_end < vsync_start || vsync_end > vtotal)
@@ -939,7 +939,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
- (vsync_start - 1) | ((vsync_end - 1) << 16));
+ VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
}
}
@@ -962,7 +962,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
- (vactive - 1) | ((vtotal - 1) << 16));
+ VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
}
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index ef0c7f5b0ad6..8f2ebead0826 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -698,11 +698,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
- vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
- vactive = (save_vtotal & 0x7ff) + 1;
+ vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
+ vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
- vblank_start = (vblank & 0xfff) + 1;
- vblank_end = ((vblank >> 16) & 0xfff) + 1;
+ vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
+ vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
/* Set the border color to purple. */
intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
@@ -732,11 +732,12 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
- u32 vsync_start = (vsync & 0xffff) + 1;
+ u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
vblank_start = vsync_start;
intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
- (vblank_start - 1) | ((vblank_end - 1) << 16));
+ VBLANK_START(vblank_start - 1) |
+ VBLANK_END(vblank_end - 1));
restore_vblank = true;
}
/* sample in the vertical border, selecting the larger one */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ac021ca88e3c..1d92a789baab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2848,18 +2848,24 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
vsyncshift);
intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
- (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
+ HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
+ HTOTAL(adjusted_mode->crtc_htotal - 1));
intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
- (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
+ HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
+ HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
- (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
+ HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
+ HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
- (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
+ VACTIVE(adjusted_mode->crtc_vdisplay - 1) |
+ VTOTAL(crtc_vtotal - 1));
intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
- (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
+ VBLANK_START(adjusted_mode->crtc_vblank_start - 1) |
+ VBLANK_END(crtc_vblank_end - 1));
intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
- (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
+ VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
+ VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
/* Workaround: when the EDP input selection is B, the VTOTAL_B must be
* programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
@@ -2912,30 +2918,31 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
u32 tmp;
tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
- adjusted_mode->crtc_hdisplay = (tmp & 0xffff) + 1;
- adjusted_mode->crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
+ adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
- adjusted_mode->crtc_hblank_start = (tmp & 0xffff) + 1;
- adjusted_mode->crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
+ adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
}
+
tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
- adjusted_mode->crtc_hsync_start = (tmp & 0xffff) + 1;
- adjusted_mode->crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
+ adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
- adjusted_mode->crtc_vdisplay = (tmp & 0xffff) + 1;
- adjusted_mode->crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
+ adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
- adjusted_mode->crtc_vblank_start = (tmp & 0xffff) + 1;
- adjusted_mode->crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
+ adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
}
tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
- adjusted_mode->crtc_vsync_start = (tmp & 0xffff) + 1;
- adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
+ adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
+ adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
if (intel_pipe_is_interlaced(pipe_config)) {
adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
@@ -8816,13 +8823,20 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
PLL_REF_INPUT_DREFCLK |
DPLL_VCO_ENABLE;
- intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
- intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
- intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), (656 - 1) | ((752 - 1) << 16));
- intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
- intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
- intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), (490 - 1) | ((492 - 1) << 16));
- intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
+ intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
+ HACTIVE(640 - 1) | HTOTAL(800 - 1));
+ intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
+ HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
+ intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
+ HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
+ intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
+ VACTIVE(480 - 1) | VTOTAL(525 - 1));
+ intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
+ VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
+ intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
+ VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
+ intel_de_write(dev_priv, PIPESRC(pipe),
+ PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
intel_de_write(dev_priv, FP0(pipe), fp);
intel_de_write(dev_priv, FP1(pipe), fp);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 23886356af35..c5e073af983a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1913,11 +1913,35 @@
/* Pipe/transcoder A timing regs */
#define _TRANS_HTOTAL_A 0x60000
+#define HTOTAL_MASK REG_GENMASK(31, 16)
+#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
+#define HACTIVE_MASK REG_GENMASK(15, 0)
+#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
#define _TRANS_HBLANK_A 0x60004
+#define HBLANK_END_MASK REG_GENMASK(31, 16)
+#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
+#define HBLANK_START_MASK REG_GENMASK(15, 0)
+#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
#define _TRANS_HSYNC_A 0x60008
+#define HSYNC_END_MASK REG_GENMASK(31, 16)
+#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
+#define HSYNC_START_MASK REG_GENMASK(15, 0)
+#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
#define _TRANS_VTOTAL_A 0x6000c
+#define VTOTAL_MASK REG_GENMASK(31, 16)
+#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
+#define VACTIVE_MASK REG_GENMASK(15, 0)
+#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
#define _TRANS_VBLANK_A 0x60010
+#define VBLANK_END_MASK REG_GENMASK(31, 16)
+#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
+#define VBLANK_START_MASK REG_GENMASK(15, 0)
+#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
#define _TRANS_VSYNC_A 0x60014
+#define VSYNC_END_MASK REG_GENMASK(31, 16)
+#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
+#define VSYNC_START_MASK REG_GENMASK(15, 0)
+#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
#define _TRANS_EXITLINE_A 0x60018
#define _PIPEASRC 0x6001c
#define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks
2023-02-13 22:52 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks Ville Syrjala
@ 2023-02-14 10:32 ` Jani Nikula
2023-02-14 10:34 ` Jani Nikula
2023-02-14 10:57 ` Ville Syrjälä
0 siblings, 2 replies; 27+ messages in thread
From: Jani Nikula @ 2023-02-14 10:32 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Define the contents of the transcoder timing registers using
> REG_GENMASK() & co. For ease of maintenance let's just define
> the bitmasks with the full 16bit width (also used by the
> current hand rolled stuff) even though not all bits are actually
> used. None of the unsued bits have ever contained anything.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 10 +--
> drivers/gpu/drm/i915/display/intel_crt.c | 13 ++--
> drivers/gpu/drm/i915/display/intel_display.c | 64 ++++++++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 24 ++++++++
> 4 files changed, 75 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 07897d6f9c53..def3aff4d717 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -888,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
> - (hactive - 1) | ((htotal - 1) << 16));
> + HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
> }
>
> /* TRANS_HSYNC register to be programmed only for video mode */
> @@ -911,7 +911,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
> - (hsync_start - 1) | ((hsync_end - 1) << 16));
> + HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
> }
> }
>
> @@ -925,7 +925,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> * For interlace mode: program required pixel minus 2
> */
> intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
> - (vactive - 1) | ((vtotal - 1) << 16));
> + VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
> }
>
> if (vsync_end < vsync_start || vsync_end > vtotal)
> @@ -939,7 +939,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
> - (vsync_start - 1) | ((vsync_end - 1) << 16));
> + VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
> }
> }
>
> @@ -962,7 +962,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
> - (vactive - 1) | ((vtotal - 1) << 16));
> + VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
> }
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index ef0c7f5b0ad6..8f2ebead0826 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -698,11 +698,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
>
> - vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
> - vactive = (save_vtotal & 0x7ff) + 1;
> + vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
> + vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
>
> - vblank_start = (vblank & 0xfff) + 1;
> - vblank_end = ((vblank >> 16) & 0xfff) + 1;
> + vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
> + vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
I forget how these are defined in bspec and if the field size grows
towards later platforms... but this widens the masks. I'm guess it'll
probably read as zero anyway, but in theory that's a functional change.
BR,
Jani.
>
> /* Set the border color to purple. */
> intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
> @@ -732,11 +732,12 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> */
> if (vblank_start <= vactive && vblank_end >= vtotal) {
> u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
> - u32 vsync_start = (vsync & 0xffff) + 1;
> + u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
>
> vblank_start = vsync_start;
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> - (vblank_start - 1) | ((vblank_end - 1) << 16));
> + VBLANK_START(vblank_start - 1) |
> + VBLANK_END(vblank_end - 1));
> restore_vblank = true;
> }
> /* sample in the vertical border, selecting the larger one */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ac021ca88e3c..1d92a789baab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2848,18 +2848,24 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> vsyncshift);
>
> intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
> - (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
> + HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
> + HTOTAL(adjusted_mode->crtc_htotal - 1));
> intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
> - (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
> + HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
> + HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
> intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
> - (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
> + HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
> + HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>
> intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> - (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
> + VACTIVE(adjusted_mode->crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1));
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> - (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
> + VBLANK_START(adjusted_mode->crtc_vblank_start - 1) |
> + VBLANK_END(crtc_vblank_end - 1));
> intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> - (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
> + VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> + VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
>
> /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
> * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
> @@ -2912,30 +2918,31 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> u32 tmp;
>
> tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
> - adjusted_mode->crtc_hdisplay = (tmp & 0xffff) + 1;
> - adjusted_mode->crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
> + adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
> + adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
>
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
> - adjusted_mode->crtc_hblank_start = (tmp & 0xffff) + 1;
> - adjusted_mode->crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
> + adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
> + adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
> }
> +
> tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
> - adjusted_mode->crtc_hsync_start = (tmp & 0xffff) + 1;
> - adjusted_mode->crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
> + adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
> + adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
>
> tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> - adjusted_mode->crtc_vdisplay = (tmp & 0xffff) + 1;
> - adjusted_mode->crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
> + adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
> + adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> - adjusted_mode->crtc_vblank_start = (tmp & 0xffff) + 1;
> - adjusted_mode->crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
> + adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
> + adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
> }
> tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
> - adjusted_mode->crtc_vsync_start = (tmp & 0xffff) + 1;
> - adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
> + adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
> + adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
>
> if (intel_pipe_is_interlaced(pipe_config)) {
> adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
> @@ -8816,13 +8823,20 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> PLL_REF_INPUT_DREFCLK |
> DPLL_VCO_ENABLE;
>
> - intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
> - intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
> - intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), (656 - 1) | ((752 - 1) << 16));
> - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
> - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
> - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), (490 - 1) | ((492 - 1) << 16));
> - intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
> + intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
> + HACTIVE(640 - 1) | HTOTAL(800 - 1));
> + intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
> + HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
> + intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
> + HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
> + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> + VACTIVE(480 - 1) | VTOTAL(525 - 1));
> + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> + VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
> + intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> + VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
> + intel_de_write(dev_priv, PIPESRC(pipe),
> + PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
>
> intel_de_write(dev_priv, FP0(pipe), fp);
> intel_de_write(dev_priv, FP1(pipe), fp);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 23886356af35..c5e073af983a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1913,11 +1913,35 @@
>
> /* Pipe/transcoder A timing regs */
> #define _TRANS_HTOTAL_A 0x60000
> +#define HTOTAL_MASK REG_GENMASK(31, 16)
> +#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
> +#define HACTIVE_MASK REG_GENMASK(15, 0)
> +#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
> #define _TRANS_HBLANK_A 0x60004
> +#define HBLANK_END_MASK REG_GENMASK(31, 16)
> +#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
> +#define HBLANK_START_MASK REG_GENMASK(15, 0)
> +#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
> #define _TRANS_HSYNC_A 0x60008
> +#define HSYNC_END_MASK REG_GENMASK(31, 16)
> +#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
> +#define HSYNC_START_MASK REG_GENMASK(15, 0)
> +#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
> #define _TRANS_VTOTAL_A 0x6000c
> +#define VTOTAL_MASK REG_GENMASK(31, 16)
> +#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
> +#define VACTIVE_MASK REG_GENMASK(15, 0)
> +#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
> #define _TRANS_VBLANK_A 0x60010
> +#define VBLANK_END_MASK REG_GENMASK(31, 16)
> +#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
> +#define VBLANK_START_MASK REG_GENMASK(15, 0)
> +#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
> #define _TRANS_VSYNC_A 0x60014
> +#define VSYNC_END_MASK REG_GENMASK(31, 16)
> +#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
> +#define VSYNC_START_MASK REG_GENMASK(15, 0)
> +#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
> #define _TRANS_EXITLINE_A 0x60018
> #define _PIPEASRC 0x6001c
> #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks
2023-02-14 10:32 ` Jani Nikula
@ 2023-02-14 10:34 ` Jani Nikula
2023-02-14 10:57 ` Ville Syrjälä
1 sibling, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2023-02-14 10:34 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 14 Feb 2023, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Define the contents of the transcoder timing registers using
>> REG_GENMASK() & co. For ease of maintenance let's just define
>> the bitmasks with the full 16bit width (also used by the
>> current hand rolled stuff) even though not all bits are actually
>> used. None of the unsued bits have ever contained anything.
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/display/icl_dsi.c | 10 +--
>> drivers/gpu/drm/i915/display/intel_crt.c | 13 ++--
>> drivers/gpu/drm/i915/display/intel_display.c | 64 ++++++++++++--------
>> drivers/gpu/drm/i915/i915_reg.h | 24 ++++++++
>> 4 files changed, 75 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index 07897d6f9c53..def3aff4d717 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -888,7 +888,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>> for_each_dsi_port(port, intel_dsi->ports) {
>> dsi_trans = dsi_port_to_transcoder(port);
>> intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
>> - (hactive - 1) | ((htotal - 1) << 16));
>> + HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
>> }
>>
>> /* TRANS_HSYNC register to be programmed only for video mode */
>> @@ -911,7 +911,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>> for_each_dsi_port(port, intel_dsi->ports) {
>> dsi_trans = dsi_port_to_transcoder(port);
>> intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
>> - (hsync_start - 1) | ((hsync_end - 1) << 16));
>> + HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
>> }
>> }
>>
>> @@ -925,7 +925,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>> * For interlace mode: program required pixel minus 2
>> */
>> intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
>> - (vactive - 1) | ((vtotal - 1) << 16));
>> + VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
>> }
>>
>> if (vsync_end < vsync_start || vsync_end > vtotal)
>> @@ -939,7 +939,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>> for_each_dsi_port(port, intel_dsi->ports) {
>> dsi_trans = dsi_port_to_transcoder(port);
>> intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
>> - (vsync_start - 1) | ((vsync_end - 1) << 16));
>> + VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
>> }
>> }
>>
>> @@ -962,7 +962,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>> for_each_dsi_port(port, intel_dsi->ports) {
>> dsi_trans = dsi_port_to_transcoder(port);
>> intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
>> - (vactive - 1) | ((vtotal - 1) << 16));
>> + VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
>> }
>> }
>> }
>> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
>> index ef0c7f5b0ad6..8f2ebead0826 100644
>> --- a/drivers/gpu/drm/i915/display/intel_crt.c
>> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
>> @@ -698,11 +698,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>> save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
>> vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
>>
>> - vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
>> - vactive = (save_vtotal & 0x7ff) + 1;
>> + vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
>> + vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
>>
>> - vblank_start = (vblank & 0xfff) + 1;
>> - vblank_end = ((vblank >> 16) & 0xfff) + 1;
>> + vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
>> + vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
>
> I forget how these are defined in bspec and if the field size grows
> towards later platforms... but this widens the masks. I'm guess it'll
> probably read as zero anyway, but in theory that's a functional change.
Regardless, up to and including this patch,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> BR,
> Jani.
>
>>
>> /* Set the border color to purple. */
>> intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
>> @@ -732,11 +732,12 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
>> */
>> if (vblank_start <= vactive && vblank_end >= vtotal) {
>> u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
>> - u32 vsync_start = (vsync & 0xffff) + 1;
>> + u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
>>
>> vblank_start = vsync_start;
>> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
>> - (vblank_start - 1) | ((vblank_end - 1) << 16));
>> + VBLANK_START(vblank_start - 1) |
>> + VBLANK_END(vblank_end - 1));
>> restore_vblank = true;
>> }
>> /* sample in the vertical border, selecting the larger one */
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index ac021ca88e3c..1d92a789baab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -2848,18 +2848,24 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
>> vsyncshift);
>>
>> intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
>> - (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << 16));
>> + HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
>> + HTOTAL(adjusted_mode->crtc_htotal - 1));
>> intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
>> - (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - 1) << 16));
>> + HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
>> + HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
>> intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
>> - (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) << 16));
>> + HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
>> + HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>>
>> intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
>> - (adjusted_mode->crtc_vdisplay - 1) | ((crtc_vtotal - 1) << 16));
>> + VACTIVE(adjusted_mode->crtc_vdisplay - 1) |
>> + VTOTAL(crtc_vtotal - 1));
>> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
>> - (adjusted_mode->crtc_vblank_start - 1) | ((crtc_vblank_end - 1) << 16));
>> + VBLANK_START(adjusted_mode->crtc_vblank_start - 1) |
>> + VBLANK_END(crtc_vblank_end - 1));
>> intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
>> - (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16));
>> + VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
>> + VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
>>
>> /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
>> * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
>> @@ -2912,30 +2918,31 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
>> u32 tmp;
>>
>> tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
>> - adjusted_mode->crtc_hdisplay = (tmp & 0xffff) + 1;
>> - adjusted_mode->crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
>> + adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
>> + adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
>>
>> if (!transcoder_is_dsi(cpu_transcoder)) {
>> tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
>> - adjusted_mode->crtc_hblank_start = (tmp & 0xffff) + 1;
>> - adjusted_mode->crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
>> + adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
>> + adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
>> }
>> +
>> tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
>> - adjusted_mode->crtc_hsync_start = (tmp & 0xffff) + 1;
>> - adjusted_mode->crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
>> + adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
>> + adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
>>
>> tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
>> - adjusted_mode->crtc_vdisplay = (tmp & 0xffff) + 1;
>> - adjusted_mode->crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
>> + adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
>> + adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>>
>> if (!transcoder_is_dsi(cpu_transcoder)) {
>> tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
>> - adjusted_mode->crtc_vblank_start = (tmp & 0xffff) + 1;
>> - adjusted_mode->crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
>> + adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
>> + adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
>> }
>> tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
>> - adjusted_mode->crtc_vsync_start = (tmp & 0xffff) + 1;
>> - adjusted_mode->crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
>> + adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
>> + adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
>>
>> if (intel_pipe_is_interlaced(pipe_config)) {
>> adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
>> @@ -8816,13 +8823,20 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
>> PLL_REF_INPUT_DREFCLK |
>> DPLL_VCO_ENABLE;
>>
>> - intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
>> - intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), (640 - 1) | ((800 - 1) << 16));
>> - intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), (656 - 1) | ((752 - 1) << 16));
>> - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
>> - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), (480 - 1) | ((525 - 1) << 16));
>> - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), (490 - 1) | ((492 - 1) << 16));
>> - intel_de_write(dev_priv, PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1));
>> + intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
>> + HACTIVE(640 - 1) | HTOTAL(800 - 1));
>> + intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
>> + HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
>> + intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
>> + HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
>> + intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
>> + VACTIVE(480 - 1) | VTOTAL(525 - 1));
>> + intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
>> + VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
>> + intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
>> + VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
>> + intel_de_write(dev_priv, PIPESRC(pipe),
>> + PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
>>
>> intel_de_write(dev_priv, FP0(pipe), fp);
>> intel_de_write(dev_priv, FP1(pipe), fp);
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 23886356af35..c5e073af983a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1913,11 +1913,35 @@
>>
>> /* Pipe/transcoder A timing regs */
>> #define _TRANS_HTOTAL_A 0x60000
>> +#define HTOTAL_MASK REG_GENMASK(31, 16)
>> +#define HTOTAL(htotal) REG_FIELD_PREP(HTOTAL_MASK, (htotal))
>> +#define HACTIVE_MASK REG_GENMASK(15, 0)
>> +#define HACTIVE(hdisplay) REG_FIELD_PREP(HACTIVE_MASK, (hdisplay))
>> #define _TRANS_HBLANK_A 0x60004
>> +#define HBLANK_END_MASK REG_GENMASK(31, 16)
>> +#define HBLANK_END(hblank_end) REG_FIELD_PREP(HBLANK_END_MASK, (hblank_end))
>> +#define HBLANK_START_MASK REG_GENMASK(15, 0)
>> +#define HBLANK_START(hblank_start) REG_FIELD_PREP(HBLANK_START_MASK, (hblank_start))
>> #define _TRANS_HSYNC_A 0x60008
>> +#define HSYNC_END_MASK REG_GENMASK(31, 16)
>> +#define HSYNC_END(hsync_end) REG_FIELD_PREP(HSYNC_END_MASK, (hsync_end))
>> +#define HSYNC_START_MASK REG_GENMASK(15, 0)
>> +#define HSYNC_START(hsync_start) REG_FIELD_PREP(HSYNC_START_MASK, (hsync_start))
>> #define _TRANS_VTOTAL_A 0x6000c
>> +#define VTOTAL_MASK REG_GENMASK(31, 16)
>> +#define VTOTAL(vtotal) REG_FIELD_PREP(VTOTAL_MASK, (vtotal))
>> +#define VACTIVE_MASK REG_GENMASK(15, 0)
>> +#define VACTIVE(vdisplay) REG_FIELD_PREP(VACTIVE_MASK, (vdisplay))
>> #define _TRANS_VBLANK_A 0x60010
>> +#define VBLANK_END_MASK REG_GENMASK(31, 16)
>> +#define VBLANK_END(vblank_end) REG_FIELD_PREP(VBLANK_END_MASK, (vblank_end))
>> +#define VBLANK_START_MASK REG_GENMASK(15, 0)
>> +#define VBLANK_START(vblank_start) REG_FIELD_PREP(VBLANK_START_MASK, (vblank_start))
>> #define _TRANS_VSYNC_A 0x60014
>> +#define VSYNC_END_MASK REG_GENMASK(31, 16)
>> +#define VSYNC_END(vsync_end) REG_FIELD_PREP(VSYNC_END_MASK, (vsync_end))
>> +#define VSYNC_START_MASK REG_GENMASK(15, 0)
>> +#define VSYNC_START(vsync_start) REG_FIELD_PREP(VSYNC_START_MASK, (vsync_start))
>> #define _TRANS_EXITLINE_A 0x60018
>> #define _PIPEASRC 0x6001c
>> #define PIPESRC_WIDTH_MASK REG_GENMASK(31, 16)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks
2023-02-14 10:32 ` Jani Nikula
2023-02-14 10:34 ` Jani Nikula
@ 2023-02-14 10:57 ` Ville Syrjälä
1 sibling, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2023-02-14 10:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Tue, Feb 14, 2023 at 12:32:49PM +0200, Jani Nikula wrote:
> On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> > index ef0c7f5b0ad6..8f2ebead0826 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -698,11 +698,11 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> > save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
> > vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> >
> > - vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
> > - vactive = (save_vtotal & 0x7ff) + 1;
> > + vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
> > + vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
> >
> > - vblank_start = (vblank & 0xfff) + 1;
> > - vblank_end = ((vblank >> 16) & 0xfff) + 1;
> > + vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
> > + vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
>
> I forget how these are defined in bspec and if the field size grows
> towards later platforms... but this widens the masks. I'm guess it'll
> probably read as zero anyway, but in theory that's a functional change.
Missed the fact tht this used smaller masks here for these few.
But it should be all good as eveywhere else we've been using the
full 16bits, so the state checker should have spotted any extra
garbage in the high bits.
But I'll add a note to the commit message, just in case.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (8 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 09/12] drm/i915: Define transcoder timing register bitmasks Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-16 14:28 ` Jani Nikula
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
` (4 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On TGL VBLANK.VBLANK_START was the mechanism by which we can
delay the pipe's internal vblank in relation to the transcoder's
vblank. On ADL+ that no longer does anything. Instead we must
now use the new TRANS_SET_CONTEXT_LATENCY register. Program it
accordingly.
And since VBLANK.VBLANK_START is no longer used by the hardware
on ADL+ let's just zero it out to make it stand out in register
dumps. Seeing the zeroed value should hopefully remind people
to check the other register instead.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++++++++---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 1d92a789baab..92306246e907 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2821,12 +2821,14 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
enum pipe pipe = crtc->pipe;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
- u32 crtc_vtotal, crtc_vblank_end;
+ u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
int vsyncshift = 0;
/* We need to be careful not to changed the adjusted mode, for otherwise
* the hw state checker will get angry at the mismatch. */
+ crtc_vdisplay = adjusted_mode->crtc_vdisplay;
crtc_vtotal = adjusted_mode->crtc_vtotal;
+ crtc_vblank_start = adjusted_mode->crtc_vblank_start;
crtc_vblank_end = adjusted_mode->crtc_vblank_end;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
@@ -2843,6 +2845,21 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
vsyncshift += adjusted_mode->crtc_htotal;
}
+ /*
+ * VBLANK_START no longer works on ADL+, instead we must use
+ * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
+ */
+ if (DISPLAY_VER(dev_priv) >= 13) {
+ intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
+ crtc_vblank_start - crtc_vdisplay);
+
+ /*
+ * VBLANK_START not used by hw, just clear it
+ * to make it stand out in register dumps.
+ */
+ crtc_vblank_start = 1;
+ }
+
if (DISPLAY_VER(dev_priv) > 3)
intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
vsyncshift);
@@ -2858,10 +2875,10 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
- VACTIVE(adjusted_mode->crtc_vdisplay - 1) |
+ VACTIVE(crtc_vdisplay - 1) |
VTOTAL(crtc_vtotal - 1));
intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
- VBLANK_START(adjusted_mode->crtc_vblank_start - 1) |
+ VBLANK_START(crtc_vblank_start - 1) |
VBLANK_END(crtc_vblank_end - 1));
intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
@@ -2949,6 +2966,11 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_vtotal += 1;
adjusted_mode->crtc_vblank_end += 1;
}
+
+ if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
+ adjusted_mode->crtc_vblank_start =
+ adjusted_mode->crtc_vdisplay +
+ intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
}
static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
2023-02-13 22:52 ` [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+ Ville Syrjala
@ 2023-02-16 14:28 ` Jani Nikula
0 siblings, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2023-02-16 14:28 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> On TGL VBLANK.VBLANK_START was the mechanism by which we can
> delay the pipe's internal vblank in relation to the transcoder's
> vblank. On ADL+ that no longer does anything. Instead we must
> now use the new TRANS_SET_CONTEXT_LATENCY register. Program it
> accordingly.
>
> And since VBLANK.VBLANK_START is no longer used by the hardware
> on ADL+ let's just zero it out to make it stand out in register
> dumps. Seeing the zeroed value should hopefully remind people
> to check the other register instead.
The specs are a bit hazy on this one. The patch does what it says on the
box, so
Acked-by: Jani Nikula <jani.nikula@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 28 +++++++++++++++++---
> 1 file changed, 25 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 1d92a789baab..92306246e907 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2821,12 +2821,14 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> enum pipe pipe = crtc->pipe;
> enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> - u32 crtc_vtotal, crtc_vblank_end;
> + u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
> int vsyncshift = 0;
>
> /* We need to be careful not to changed the adjusted mode, for otherwise
> * the hw state checker will get angry at the mismatch. */
> + crtc_vdisplay = adjusted_mode->crtc_vdisplay;
> crtc_vtotal = adjusted_mode->crtc_vtotal;
> + crtc_vblank_start = adjusted_mode->crtc_vblank_start;
> crtc_vblank_end = adjusted_mode->crtc_vblank_end;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> @@ -2843,6 +2845,21 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> vsyncshift += adjusted_mode->crtc_htotal;
> }
>
> + /*
> + * VBLANK_START no longer works on ADL+, instead we must use
> + * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
> + */
> + if (DISPLAY_VER(dev_priv) >= 13) {
> + intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
> + crtc_vblank_start - crtc_vdisplay);
> +
> + /*
> + * VBLANK_START not used by hw, just clear it
> + * to make it stand out in register dumps.
> + */
> + crtc_vblank_start = 1;
> + }
> +
> if (DISPLAY_VER(dev_priv) > 3)
> intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
> vsyncshift);
> @@ -2858,10 +2875,10 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
>
> intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
> - VACTIVE(adjusted_mode->crtc_vdisplay - 1) |
> + VACTIVE(crtc_vdisplay - 1) |
> VTOTAL(crtc_vtotal - 1));
> intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
> - VBLANK_START(adjusted_mode->crtc_vblank_start - 1) |
> + VBLANK_START(crtc_vblank_start - 1) |
> VBLANK_END(crtc_vblank_end - 1));
> intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
> VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
> @@ -2949,6 +2966,11 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vtotal += 1;
> adjusted_mode->crtc_vblank_end += 1;
> }
> +
> + if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
> + adjusted_mode->crtc_vblank_start =
> + adjusted_mode->crtc_vdisplay +
> + intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
> }
>
> static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (9 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 10/12] drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+ Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-14 10:35 ` Jani Nikula
2023-02-20 21:29 ` Ville Syrjälä
2023-02-13 22:52 ` [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read Ville Syrjala
` (3 subsequent siblings)
14 siblings, 2 replies; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The DSI code has some local hacks to program TRANS_H/VBLANK on
TGL+ (ICL DSI transcoders didn't have these registers). That
will not work when we need to start using the delayed vblank
(for DSB purposes). Too lazy to figure out what the is going
on there, so just sprinkle FIXMEs in the hopes someone else
will spot them eventually.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 7 ++++++-
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index def3aff4d717..b5316715bb3b 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -957,7 +957,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
}
}
- /* program TRANS_VBLANK register, should be same as vtotal programmed */
+ /*
+ * program TRANS_VBLANK register, should be same as vtotal programmed
+ *
+ * FIXME get rid of these local hacks and do it right,
+ * this will not handle eg. delayed vblank correctly.
+ */
if (DISPLAY_VER(dev_priv) >= 12) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 92306246e907..4210ede5e52e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2938,6 +2938,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
+ /* FIXME TGL+ DSI transcoders have this! */
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
@@ -2952,6 +2953,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
+ /* FIXME TGL+ DSI transcoders have this! */
if (!transcoder_is_dsi(cpu_transcoder)) {
tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
@@ -2967,6 +2969,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
adjusted_mode->crtc_vblank_end += 1;
}
+ /* FIXME ADL+ DSI transcoders have this! */
if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
adjusted_mode->crtc_vblank_start =
adjusted_mode->crtc_vdisplay +
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
@ 2023-02-14 10:35 ` Jani Nikula
2023-02-20 21:29 ` Ville Syrjälä
1 sibling, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2023-02-14 10:35 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The DSI code has some local hacks to program TRANS_H/VBLANK on
> TGL+ (ICL DSI transcoders didn't have these registers). That
> will not work when we need to start using the delayed vblank
> (for DSB purposes). Too lazy to figure out what the is going
> on there, so just sprinkle FIXMEs in the hopes someone else
> will spot them eventually.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 7 ++++++-
> drivers/gpu/drm/i915/display/intel_display.c | 3 +++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index def3aff4d717..b5316715bb3b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -957,7 +957,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> }
> }
>
> - /* program TRANS_VBLANK register, should be same as vtotal programmed */
> + /*
> + * program TRANS_VBLANK register, should be same as vtotal programmed
> + *
> + * FIXME get rid of these local hacks and do it right,
> + * this will not handle eg. delayed vblank correctly.
> + */
> if (DISPLAY_VER(dev_priv) >= 12) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 92306246e907..4210ede5e52e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2938,6 +2938,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
> adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
>
> + /* FIXME TGL+ DSI transcoders have this! */
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
> adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
> @@ -2952,6 +2953,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
> adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>
> + /* FIXME TGL+ DSI transcoders have this! */
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
> @@ -2967,6 +2969,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vblank_end += 1;
> }
>
> + /* FIXME ADL+ DSI transcoders have this! */
> if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
> adjusted_mode->crtc_vblank_start =
> adjusted_mode->crtc_vdisplay +
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
2023-02-14 10:35 ` Jani Nikula
@ 2023-02-20 21:29 ` Ville Syrjälä
1 sibling, 0 replies; 27+ messages in thread
From: Ville Syrjälä @ 2023-02-20 21:29 UTC (permalink / raw)
To: intel-gfx
On Tue, Feb 14, 2023 at 12:52:57AM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The DSI code has some local hacks to program TRANS_H/VBLANK on
> TGL+ (ICL DSI transcoders didn't have these registers). That
> will not work when we need to start using the delayed vblank
> (for DSB purposes). Too lazy to figure out what the is going
> on there, so just sprinkle FIXMEs in the hopes someone else
> will spot them eventually.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 7 ++++++-
> drivers/gpu/drm/i915/display/intel_display.c | 3 +++
> 2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index def3aff4d717..b5316715bb3b 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -957,7 +957,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> }
> }
>
> - /* program TRANS_VBLANK register, should be same as vtotal programmed */
> + /*
> + * program TRANS_VBLANK register, should be same as vtotal programmed
> + *
> + * FIXME get rid of these local hacks and do it right,
> + * this will not handle eg. delayed vblank correctly.
> + */
> if (DISPLAY_VER(dev_priv) >= 12) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 92306246e907..4210ede5e52e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2938,6 +2938,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
> adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
>
> + /* FIXME TGL+ DSI transcoders have this! */
Actually no. They do not. Only TRANS_VBLANK got added to the DSI
transcoders on TGL.
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
> adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
> @@ -2952,6 +2953,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
> adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
>
> + /* FIXME TGL+ DSI transcoders have this! */
> if (!transcoder_is_dsi(cpu_transcoder)) {
> tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
> adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
> @@ -2967,6 +2969,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc,
> adjusted_mode->crtc_vblank_end += 1;
> }
>
> + /* FIXME ADL+ DSI transcoders have this! */
This seems to be a lie too.
I dropped these two FIXMEs and pushed the rest. Thanks for the
review.
> if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
> adjusted_mode->crtc_vblank_start =
> adjusted_mode->crtc_vdisplay +
> --
> 2.39.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (10 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 11/12] drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess Ville Syrjala
@ 2023-02-13 22:52 ` Ville Syrjala
2023-02-14 10:38 ` Jani Nikula
2023-02-13 23:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Transcoder timing stuff Patchwork
` (2 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: Ville Syrjala @ 2023-02-13 22:52 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We just wrote the EDP transcoder's VTOTAL register a few lines
earlier, so instead of reading it back out again let's just
generate the same value for the transocder B/C register.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 4210ede5e52e..894f3098d9be 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2891,8 +2891,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
(pipe == PIPE_B || pipe == PIPE_C))
intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
- intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
-
+ VACTIVE(crtc_vdisplay - 1) |
+ VTOTAL(crtc_vtotal - 1));
}
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
--
2.39.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* Re: [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read
2023-02-13 22:52 ` [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read Ville Syrjala
@ 2023-02-14 10:38 ` Jani Nikula
0 siblings, 0 replies; 27+ messages in thread
From: Jani Nikula @ 2023-02-14 10:38 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Tue, 14 Feb 2023, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We just wrote the EDP transcoder's VTOTAL register a few lines
> earlier, so instead of reading it back out again let's just
> generate the same value for the transocder B/C register.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4210ede5e52e..894f3098d9be 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2891,8 +2891,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
> if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
> (pipe == PIPE_B || pipe == PIPE_C))
> intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
> - intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)));
> -
> + VACTIVE(crtc_vdisplay - 1) |
> + VTOTAL(crtc_vtotal - 1));
> }
>
> static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 27+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Transcoder timing stuff
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (11 preceding siblings ...)
2023-02-13 22:52 ` [Intel-gfx] [PATCH 12/12] drm/i915: Remove pointless register read Ville Syrjala
@ 2023-02-13 23:24 ` Patchwork
2023-02-13 23:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-02-14 2:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-02-13 23:24 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Transcoder timing stuff
URL : https://patchwork.freedesktop.org/series/113974/
State : warning
== Summary ==
Error: dim checkpatch failed
29054f91dc49 drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock()
90b8f6819152 drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock()
7fb6bce53da6 drm/i915: Give CPU transcoder timing registers TRANS_ prefix
cbfdc446a13d drm/i915: s/PIPECONF/TRANSCONF/
-:120: WARNING:LINE_SPACING: Missing a blank line after declarations
#120: FILE: drivers/gpu/drm/i915/display/intel_display.c:422:
+ u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
+ cur_state = !!(val & TRANSCONF_ENABLE);
-:183: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#183: FILE: drivers/gpu/drm/i915/display/intel_display.c:2900:
+ return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
-:186: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#186: FILE: drivers/gpu/drm/i915/display/intel_display.c:2902:
+ return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
-:826: WARNING:LONG_LINE: line length of 128 exceeds 100 columns
#826: FILE: drivers/gpu/drm/i915/i915_reg.h:3453:
+#define TRANSCONF_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANSCONF_FRAME_START_DELAY_MASK, (x)) /* pre-hsw: 0-3 */
-:833: WARNING:LONG_LINE_COMMENT: line length of 110 exceeds 100 columns
#833: FILE: drivers/gpu/drm/i915/i915_reg.h:3460:
+#define TRANSCONF_GAMMA_MODE_12BIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 2) /* ilk-ivb */
-:834: WARNING:LONG_LINE_COMMENT: line length of 106 exceeds 100 columns
#834: FILE: drivers/gpu/drm/i915/i915_reg.h:3461:
+#define TRANSCONF_GAMMA_MODE_SPLIT REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, 3) /* ivb */
-:835: WARNING:LONG_LINE_COMMENT: line length of 130 exceeds 100 columns
#835: FILE: drivers/gpu/drm/i915/i915_reg.h:3462:
+#define TRANSCONF_GAMMA_MODE(x) REG_FIELD_PREP(TRANSCONF_GAMMA_MODE_MASK_ILK, (x)) /* pass in GAMMA_MODE_MODE_* */
-:838: WARNING:LONG_LINE_COMMENT: line length of 115 exceeds 100 columns
#838: FILE: drivers/gpu/drm/i915/i915_reg.h:3465:
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT_PANEL REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 4) /* gen4 only */
-:839: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#839: FILE: drivers/gpu/drm/i915/i915_reg.h:3466:
+#define TRANSCONF_INTERLACE_W_SYNC_SHIFT REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 5) /* gen4 only */
-:841: WARNING:LONG_LINE_COMMENT: line length of 107 exceeds 100 columns
#841: FILE: drivers/gpu/drm/i915/i915_reg.h:3468:
+#define TRANSCONF_INTERLACE_FIELD_0_ONLY REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK, 7) /* gen3 only */
-:880: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns
#880: FILE: drivers/gpu/drm/i915/i915_reg.h:3478:
+#define TRANSCONF_INTERLACE_IF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 4) /* ilk/snb only */
-:881: WARNING:LONG_LINE_COMMENT: line length of 114 exceeds 100 columns
#881: FILE: drivers/gpu/drm/i915/i915_reg.h:3479:
+#define TRANSCONF_INTERLACE_PF_ID_DBL_ILK REG_FIELD_PREP(TRANSCONF_INTERLACE_MASK_ILK, 5) /* ilk/snb only */
-:889: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#889: FILE: drivers/gpu/drm/i915/i915_reg.h:3487:
+#define TRANSCONF_OUTPUT_COLORSPACE_RGB REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 0) /* ilk-ivb */
-:890: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#890: FILE: drivers/gpu/drm/i915/i915_reg.h:3488:
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV601 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 1) /* ilk-ivb */
-:891: WARNING:LONG_LINE_COMMENT: line length of 113 exceeds 100 columns
#891: FILE: drivers/gpu/drm/i915/i915_reg.h:3489:
+#define TRANSCONF_OUTPUT_COLORSPACE_YUV709 REG_FIELD_PREP(TRANSCONF_OUTPUT_COLORSPACE_MASK, 2) /* ilk-ivb */
total: 0 errors, 15 warnings, 0 checks, 819 lines checked
a14b1fc40c0b drm/i915: Dump blanking start/end
8797c05fff74 drm/i915: Define the "unmodified vblank" interrupt bit
c4734266bd12 drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY
99cb9b3ea1a8 drm/i915: Add local adjusted_mode variable
f165b7be5012 drm/i915: Define transcoder timing register bitmasks
6c8a94324c47 drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
92ecde8830fd drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
dc709edac43d drm/i915: Remove pointless register read
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Transcoder timing stuff
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (12 preceding siblings ...)
2023-02-13 23:24 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Transcoder timing stuff Patchwork
@ 2023-02-13 23:41 ` Patchwork
2023-02-14 2:34 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-02-13 23:41 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 3799 bytes --]
== Series Details ==
Series: drm/i915: Transcoder timing stuff
URL : https://patchwork.freedesktop.org/series/113974/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12734 -> Patchwork_113974v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/index.html
Participating hosts (39 -> 37)
------------------------------
Missing (2): fi-kbl-soraka fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_113974v1 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-rpls-1}: [ABORT][1] ([i915#6311]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/bat-rpls-1/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: [DMESG-FAIL][3] ([i915#5334]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [DMESG-WARN][5] ([i915#8073]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
[i915#8073]: https://gitlab.freedesktop.org/drm/intel/issues/8073
Build changes
-------------
* Linux: CI_DRM_12734 -> Patchwork_113974v1
CI-20190529: 20190529
CI_DRM_12734: ffa7027c353c6821636559f42584dd11f527b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113974v1: ffa7027c353c6821636559f42584dd11f527b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
889cd17de917 drm/i915: Remove pointless register read
761aa5806d17 drm/i915: Sprinkle some FIXMEs about TGL+ DSI transcoder timing mess
62332cb0192d drm/i915: Configure TRANS_SET_CONTEXT_LATENCY correctly on ADL+
a0acdae8655d drm/i915: Define transcoder timing register bitmasks
9e57f957ca05 drm/i915: Add local adjusted_mode variable
724998b8ebe7 drm/i915/psr: Stop clobbering TRANS_SET_CONTEXT_LATENCY
31848145a8d2 drm/i915: Define the "unmodified vblank" interrupt bit
f9d9e1e0118b drm/i915: Dump blanking start/end
ee5a419f33be drm/i915: s/PIPECONF/TRANSCONF/
a911344d5fe8 drm/i915: Give CPU transcoder timing registers TRANS_ prefix
476bd003a4bd drm/i915: Flatten intel_ddi_{enable, disable}_transcoder_clock()
97391c40a064 drm/i915: Rename intel_ddi_{enable, disable}_pipe_clock()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/index.html
[-- Attachment #2: Type: text/html, Size: 4136 bytes --]
^ permalink raw reply [flat|nested] 27+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Transcoder timing stuff
2023-02-13 22:52 [Intel-gfx] [PATCH 00/12] drm/i915: Transcoder timing stuff Ville Syrjala
` (13 preceding siblings ...)
2023-02-13 23:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-02-14 2:34 ` Patchwork
14 siblings, 0 replies; 27+ messages in thread
From: Patchwork @ 2023-02-14 2:34 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 20153 bytes --]
== Series Details ==
Series: drm/i915: Transcoder timing stuff
URL : https://patchwork.freedesktop.org/series/113974/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_12734_full -> Patchwork_113974v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/index.html
Participating hosts (11 -> 10)
------------------------------
Missing (1): shard-rkl0
New tests
---------
New tests have been introduced between CI_DRM_12734_full and Patchwork_113974v1_full:
### New IGT tests (1) ###
* igt@kms_cursor_edge_walk@64x64-top-bottom@pipe-b-edp-1:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_113974v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@in-flight-contexts-immediate:
- shard-apl: [PASS][1] -> [TIMEOUT][2] ([i915#3063])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-apl6/igt@gem_eio@in-flight-contexts-immediate.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-apl1/igt@gem_eio@in-flight-contexts-immediate.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-apl: [PASS][3] -> [FAIL][4] ([i915#2842])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-apl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-apl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#4528] / [i915#4817])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-snb6/igt@i915_suspend@basic-s3-without-i915.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-snb5/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-glk1/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_ccs.html
* igt@kms_color@ctm-max@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [SKIP][8] ([fdo#109271]) +25 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-snb1/igt@kms_color@ctm-max@pipe-a-hdmi-a-1.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#72])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions:
- shard-apl: [PASS][11] -> [FAIL][12] ([i915#2346])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
- shard-glk: [PASS][13] -> [FAIL][14] ([i915#2346])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-glk6/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][15] ([i915#5465]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
#### Possible fixes ####
* igt@gem_exec_endless@dispatch@bcs0:
- {shard-rkl}: [SKIP][16] ([i915#6247]) -> [PASS][17]
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-5/igt@gem_exec_endless@dispatch@bcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-3/igt@gem_exec_endless@dispatch@bcs0.html
* igt@gem_exec_fair@basic-throttle@rcs0:
- shard-glk: [FAIL][18] ([i915#2842]) -> [PASS][19]
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-glk9/igt@gem_exec_fair@basic-throttle@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- {shard-rkl}: [SKIP][20] ([i915#3281]) -> [PASS][21] +6 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-2/igt@gem_exec_reloc@basic-write-read-noreloc.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-5/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- {shard-rkl}: [SKIP][22] ([i915#3282]) -> [PASS][23] +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gen9_exec_parse@batch-invalid-length:
- {shard-rkl}: [SKIP][24] ([i915#2527]) -> [PASS][25] +2 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-4/igt@gen9_exec_parse@batch-invalid-length.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-5/igt@gen9_exec_parse@batch-invalid-length.html
* igt@i915_hangman@engine-engine-error@bcs0:
- {shard-rkl}: [SKIP][26] ([i915#6258]) -> [PASS][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-5/igt@i915_hangman@engine-engine-error@bcs0.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-1/igt@i915_hangman@engine-engine-error@bcs0.html
* igt@i915_pm_sseu@full-enable:
- {shard-rkl}: [SKIP][28] ([i915#4387]) -> [PASS][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-4/igt@i915_pm_sseu@full-enable.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-5/igt@i915_pm_sseu@full-enable.html
* igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs:
- {shard-rkl}: [SKIP][30] ([i915#1845] / [i915#4098]) -> [PASS][31] +22 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-4/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-6/igt@kms_ccs@pipe-b-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][32] ([i915#2122]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-glk3/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-glk1/igt@kms_flip@2x-flip-vs-blocking-wf-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2:
- shard-glk: [FAIL][34] ([i915#79]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-glk2/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a2.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite:
- {shard-rkl}: [SKIP][36] ([i915#1849] / [i915#4098]) -> [PASS][37] +17 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_plane@plane-panning-bottom-right@pipe-a-planes:
- {shard-rkl}: [SKIP][38] ([i915#1849]) -> [PASS][39] +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-3/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right@pipe-a-planes.html
* igt@kms_psr@cursor_blt:
- {shard-rkl}: [SKIP][40] ([i915#1072]) -> [PASS][41] +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-4/igt@kms_psr@cursor_blt.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-6/igt@kms_psr@cursor_blt.html
* igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b:
- {shard-rkl}: [SKIP][42] ([i915#4098]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-3/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pageflip-windowed-pipe-b.html
* igt@prime_vgem@basic-fence-flip:
- {shard-rkl}: [SKIP][44] ([fdo#109295] / [i915#3708] / [i915#4098]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-3/igt@prime_vgem@basic-fence-flip.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-read:
- {shard-rkl}: [SKIP][46] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12734/shard-rkl-2/igt@prime_vgem@basic-read.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/shard-rkl-5/igt@prime_vgem@basic-read.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4859]: https://gitlab.freedesktop.org/drm/intel/issues/4859
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4884]: https://gitlab.freedesktop.org/drm/intel/issues/4884
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
[i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
[i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
[i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
[i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
[i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
[i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7949]: https://gitlab.freedesktop.org/drm/intel/issues/7949
[i915#7957]: https://gitlab.freedesktop.org/drm/intel/issues/7957
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8018]: https://gitlab.freedesktop.org/drm/intel/issues/8018
[i915#8150]: https://gitlab.freedesktop.org/drm/intel/issues/8150
Build changes
-------------
* Linux: CI_DRM_12734 -> Patchwork_113974v1
CI-20190529: 20190529
CI_DRM_12734: ffa7027c353c6821636559f42584dd11f527b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7160: 45da871dd2684227e93a2fc002b87dfc58bd5fd9 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_113974v1: ffa7027c353c6821636559f42584dd11f527b0e0 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113974v1/index.html
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