From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate
Date: Tue, 25 Jan 2022 07:35:08 +0200 [thread overview]
Message-ID: <8735lc2x9v.fsf@intel.com> (raw)
In-Reply-To: <20220124193136.2397-1-ville.syrjala@linux.intel.com>
On Mon, 24 Jan 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Use DISPLAY_VER rather than GRAPHICS_VER to determine
> availability of display hardware features.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
On both patches,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 44c1f98144b4..e2b8409f9174 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1463,8 +1463,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
> (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
>
> -#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >= 4)
> -#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >= 11 || \
> +#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >= 4)
> +#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >= 11 || \
> IS_GEMINILAKE(dev_priv) || \
> IS_KABYLAKE(dev_priv))
>
> @@ -1476,9 +1476,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
> #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
>
> -#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2)
> +#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2)
> #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask != 0)
> -#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_priv) >= 7)
> +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_priv) >= 7)
>
> #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
>
> @@ -1491,7 +1491,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
> #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
> #define HAS_PSR_HW_TRACKING(dev_priv) \
> (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
> -#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >= 12)
> +#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >= 12)
> #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
>
> #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
> @@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc)
>
> -#define HAS_MSO(i915) (GRAPHICS_VER(i915) >= 12)
> +#define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12)
>
> #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
> #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
> @@ -1535,7 +1535,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch)
>
> -#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10))
> +#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10))
>
> /* DPF == dynamic parity feature */
> #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
> @@ -1549,7 +1549,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
>
> #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
>
> -#define HAS_VRR(i915) (GRAPHICS_VER(i915) >= 11)
> +#define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11)
>
> #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5)
>
> @@ -1579,7 +1579,7 @@ i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p);
>
> static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
> {
> - return GRAPHICS_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
> + return DISPLAY_VER(dev_priv) >= 6 && intel_vtd_active(dev_priv);
> }
>
> static inline bool
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-01-25 5:35 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-24 19:31 [Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate Ville Syrjala
2022-01-24 19:31 ` [Intel-gfx] [PATCH 2/2] drm/i915: Introduce ilk_pch_pre_enable() Ville Syrjala
2022-01-25 0:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate Patchwork
2022-01-25 0:04 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-01-25 0:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-01-25 5:35 ` Jani Nikula [this message]
2022-01-25 6:24 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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