From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5D6B0C433EF for ; Tue, 25 Jan 2022 05:35:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6328A10E4D0; Tue, 25 Jan 2022 05:35:26 +0000 (UTC) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8D05C10E4D0 for ; Tue, 25 Jan 2022 05:35:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1643088925; x=1674624925; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=+pKUBH2WUIkHN21c0rKaoS8ywuYBkH7t3yOEMfB7/sQ=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: s/GRAPHICS_VER/DISPLAY_VER/ where appropriate X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Mon, 24 Jan 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Use DISPLAY_VER rather than GRAPHICS_VER to determine > availability of display hardware features. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 On both patches, Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_drv.h | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 44c1f98144b4..e2b8409f9174 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1463,8 +1463,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ > (IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) >=20=20 > -#define HAS_GMBUS_IRQ(dev_priv) (GRAPHICS_VER(dev_priv) >=3D 4) > -#define HAS_GMBUS_BURST_READ(dev_priv) (GRAPHICS_VER(dev_priv) >=3D 11 |= | \ > +#define HAS_GMBUS_IRQ(dev_priv) (DISPLAY_VER(dev_priv) >=3D 4) > +#define HAS_GMBUS_BURST_READ(dev_priv) (DISPLAY_VER(dev_priv) >=3D 11 ||= \ > IS_GEMINILAKE(dev_priv) || \ > IS_KABYLAKE(dev_priv)) >=20=20 > @@ -1476,9 +1476,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_t= v) > #define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_ho= tplug) >=20=20 > -#define HAS_FW_BLC(dev_priv) (GRAPHICS_VER(dev_priv) > 2) > +#define HAS_FW_BLC(dev_priv) (DISPLAY_VER(dev_priv) > 2) > #define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.fbc_mask !=3D 0) > -#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && GRAPHICS_VER(dev_p= riv) >=3D 7) > +#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH(dev_priv) && DISPLAY_VER(dev_pr= iv) >=3D 7) >=20=20 > #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv= )) >=20=20 > @@ -1491,7 +1491,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr) > #define HAS_PSR_HW_TRACKING(dev_priv) \ > (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking) > -#define HAS_PSR2_SEL_FETCH(dev_priv) (GRAPHICS_VER(dev_priv) >=3D 12) > +#define HAS_PSR2_SEL_FETCH(dev_priv) (DISPLAY_VER(dev_priv) >=3D 12) > #define HAS_TRANSCODER(dev_priv, trans) ((INTEL_INFO(dev_priv)->display= .cpu_transcoder_mask & BIT(trans)) !=3D 0) >=20=20 > #define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6) > @@ -1502,7 +1502,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >=20=20 > #define HAS_DMC(dev_priv) (INTEL_INFO(dev_priv)->display.has_dmc) >=20=20 > -#define HAS_MSO(i915) (GRAPHICS_VER(i915) >=3D 12) > +#define HAS_MSO(i915) (DISPLAY_VER(i915) >=3D 12) >=20=20 > #define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm) > #define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc) > @@ -1535,7 +1535,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >=20=20 > #define HAS_GMCH(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch) >=20=20 > -#define HAS_LSPCON(dev_priv) (IS_GRAPHICS_VER(dev_priv, 9, 10)) > +#define HAS_LSPCON(dev_priv) (IS_DISPLAY_VER(dev_priv, 9, 10)) >=20=20 > /* DPF =3D=3D dynamic parity feature */ > #define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf) > @@ -1549,7 +1549,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, >=20=20 > #define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != =3D 0) >=20=20 > -#define HAS_VRR(i915) (GRAPHICS_VER(i915) >=3D 11) > +#define HAS_VRR(i915) (DISPLAY_VER(i915) >=3D 11) >=20=20 > #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >=3D 5) >=20=20 > @@ -1579,7 +1579,7 @@ i915_print_iommu_status(struct drm_i915_private *i9= 15, struct drm_printer *p); >=20=20 > static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *d= ev_priv) > { > - return GRAPHICS_VER(dev_priv) >=3D 6 && intel_vtd_active(dev_priv); > + return DISPLAY_VER(dev_priv) >=3D 6 && intel_vtd_active(dev_priv); > } >=20=20 > static inline bool --=20 Jani Nikula, Intel Open Source Graphics Center