From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com, ville.syrjala@intel.com,
Deepak M <m.deepak@intel.com>,
shobhit.kumar@intel.com
Subject: Re: [GLK MIPI DSI V3 4/7] drm/i915: Set the Z inversion overlap field
Date: Wed, 18 Jan 2017 17:50:31 +0200 [thread overview]
Message-ID: <8737gg2wqg.fsf@intel.com> (raw)
In-Reply-To: <1483361668-2095-5-git-send-email-madhav.chauhan@intel.com>
On Mon, 02 Jan 2017, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> Dual link Z-inversion overlap field is present
> in MIPI_CTRL register unlike the older platforms,
> hence setting the same in this patch.
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 3ae70ae..95a6cad 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -558,12 +558,21 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder)
>
> if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> u32 temp;
> -
> - temp = I915_READ(VLV_CHICKEN_3);
> - temp &= ~PIXEL_OVERLAP_CNT_MASK |
> + if (IS_GEN9_LP(dev_priv)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + temp = I915_READ(MIPI_CTRL(port));
> + temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK |
> + intel_dsi->pixel_overlap <<
> + BXT_PIXEL_OVERLAP_CNT_SHIFT;
> + I915_WRITE(MIPI_CTRL(port), temp);
I think I'd do this where MIPI_CTRL is updated. If we set
->pixel_overlap to 0 for intel_dsi->dual_link !=
DSI_DUAL_LINK_FRONT_BACK in vbt_panel_init(), we can just write it
instead of checking dual_link.
BR,
Jani.
> + }
> + } else {
> + temp = I915_READ(VLV_CHICKEN_3);
> + temp &= ~PIXEL_OVERLAP_CNT_MASK |
> intel_dsi->pixel_overlap <<
> PIXEL_OVERLAP_CNT_SHIFT;
> - I915_WRITE(VLV_CHICKEN_3, temp);
> + I915_WRITE(VLV_CHICKEN_3, temp);
> + }
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
--
Jani Nikula, Intel Open Source Technology Center
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next prev parent reply other threads:[~2017-01-18 15:50 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-02 12:54 [GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2017-01-02 12:54 ` [GLK MIPI DSI V3 1/7] drm/i915/glk: Program dphy param reg for GLK Madhav Chauhan
2017-01-18 11:09 ` Jani Nikula
2017-01-18 14:10 ` Jani Nikula
2017-01-19 13:39 ` Chauhan, Madhav
2017-01-02 12:54 ` [GLK MIPI DSI V3 2/7] drm/i915/glk: Program new MIPI DSI PHY registers " Madhav Chauhan
2017-01-18 15:30 ` Jani Nikula
2017-01-19 6:20 ` Chauhan, Madhav
2017-01-19 9:23 ` Jani Nikula
2017-01-19 9:56 ` Chauhan, Madhav
2017-01-02 12:54 ` [GLK MIPI DSI V3 3/7] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2017-01-02 12:54 ` [GLK MIPI DSI V3 4/7] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2017-01-18 15:50 ` Jani Nikula [this message]
2017-01-20 10:06 ` Chauhan, Madhav
2017-01-02 12:54 ` [GLK MIPI DSI V3 5/7] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2017-01-02 12:54 ` [GLK MIPI DSI V3 6/7] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2017-01-02 12:54 ` [GLK MIPI DSI V3 7/7] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2017-01-02 13:23 ` ✗ Fi.CI.BAT: warning for GLK MIPI DSI VIDEO MODE PATCHES (rev3) Patchwork
2017-01-02 13:48 ` Saarinen, Jani
2017-01-31 8:34 ` [GLK MIPI DSI V3 0/7] GLK MIPI DSI VIDEO MODE PATCHES Chauhan, Madhav
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