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From: Jani Nikula <jani.nikula@intel.com>
To: Madhav Chauhan <madhav.chauhan@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: ander.conselvan.de.oliveira@intel.com,
	Deepak M <m.deepak@intel.com>,
	shobhit.kumar@intel.com
Subject: Re: [GLK MIPI DSI V2 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register
Date: Fri, 23 Dec 2016 15:54:22 +0200	[thread overview]
Message-ID: <8737helpip.fsf@intel.com> (raw)
In-Reply-To: <1481792500-30863-2-git-send-email-madhav.chauhan@intel.com>

On Thu, 15 Dec 2016, Madhav Chauhan <madhav.chauhan@intel.com> wrote:
> From: Deepak M <m.deepak@intel.com>
>
> v2: Addressed Jani's Review comments (renamed bit field macros)
>
> Signed-off-by: Deepak M <m.deepak@intel.com>
> Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>

Pushed to drm-intel-next-queued, thanks for the patch.

BR,
Jani.


> ---
>  drivers/gpu/drm/i915/i915_reg.h | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 90685d2..8e47b59 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8672,6 +8672,21 @@ enum {
>  #define  BXT_PIPE_SELECT_SHIFT				7
>  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
>  #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
> +#define  GLK_PHY_STATUS_PORT_READY			(1 << 31) /* RO */
> +#define  GLK_ULPS_NOT_ACTIVE				(1 << 30) /* RO */
> +#define  GLK_MIPIIO_RESET_RELEASED			(1 << 28)
> +#define  GLK_CLOCK_LANE_STOP_STATE			(1 << 27) /* RO */
> +#define  GLK_DATA_LANE_STOP_STATE			(1 << 26) /* RO */
> +#define  GLK_LP_WAKE					(1 << 22)
> +#define  GLK_LP11_LOW_PWR_MODE				(1 << 21)
> +#define  GLK_LP00_LOW_PWR_MODE				(1 << 20)
> +#define  GLK_FIREWALL_ENABLE				(1 << 16)
> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
> +#define  BXT_DSC_ENABLE					(1 << 3)
> +#define  BXT_RGB_FLIP					(1 << 2)
> +#define  GLK_MIPIIO_PORT_POWERED			(1 << 1) /* RO */
> +#define  GLK_MIPIIO_ENABLE				(1 << 0)
>  
>  #define _MIPIA_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb108)
>  #define _MIPIC_DATA_ADDRESS		(dev_priv->mipi_mmio_base + 0xb908)

-- 
Jani Nikula, Intel Open Source Technology Center
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Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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  reply	other threads:[~2016-12-23 13:54 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-15  9:01 [GLK MIPI DSI V2 0/9] GLK MIPI DSI VIDEO MODE PATCHES Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Madhav Chauhan
2016-12-23 13:54   ` Jani Nikula [this message]
2016-12-15  9:01 ` [GLK MIPI DSI V2 2/9] drm/i915/glk: Program new MIPI DSI PHY registers for GLK Madhav Chauhan
2016-12-22 12:02   ` Ville Syrjälä
2016-12-22 12:28     ` Jani Nikula
2016-12-23 13:57   ` Jani Nikula
2016-12-23 19:22     ` Chauhan, Madhav
2016-12-26 12:49       ` Chauhan, Madhav
2016-12-15  9:01 ` [GLK MIPI DSI V2 3/9] drm/i915/glk: Add MIPIIO Enable/disable sequence Madhav Chauhan
2016-12-23 14:09   ` Jani Nikula
2016-12-26 12:05     ` Chauhan, Madhav
2016-12-27 12:34       ` Jani Nikula
2016-12-27 13:32         ` Chauhan, Madhav
2016-12-27 14:47           ` Jani Nikula
2016-12-27 15:43             ` Chauhan, Madhav
2016-12-15  9:01 ` [GLK MIPI DSI V2 4/9] drm/i915: Set the Z inversion overlap field Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 5/9] drm/i915/glk: Add DSI PLL divider range for glk Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 6/9] drm/i915i/glk: Program MIPI_CLOCK_CTRL only for BXT Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 7/9] drm/i915/glk: Program txesc clock divider for GLK Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 8/9] drm/i915/glk: Program dphy param reg " Madhav Chauhan
2016-12-15  9:01 ` [GLK MIPI DSI V2 9/9] drm/915: Parsing the missed out DTD fields from the VBT Madhav Chauhan
2016-12-22 11:39   ` Jani Nikula
2016-12-22 13:16     ` Chauhan, Madhav
2016-12-22 13:43       ` Jani Nikula
2016-12-22 15:43         ` Chauhan, Madhav
2016-12-15  9:45 ` ✓ Fi.CI.BAT: success for GLK MIPI DSI VIDEO MODE PATCHES (rev2) Patchwork

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