From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [GLK MIPI DSI V2 1/9] drm/i915/glk: Add new bit fields in MIPI CTRL register Date: Fri, 23 Dec 2016 15:54:22 +0200 Message-ID: <8737helpip.fsf@intel.com> References: <1481792500-30863-1-git-send-email-madhav.chauhan@intel.com> <1481792500-30863-2-git-send-email-madhav.chauhan@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7E986E036 for ; Fri, 23 Dec 2016 13:54:27 +0000 (UTC) In-Reply-To: <1481792500-30863-2-git-send-email-madhav.chauhan@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Madhav Chauhan , intel-gfx@lists.freedesktop.org Cc: ander.conselvan.de.oliveira@intel.com, Deepak M , shobhit.kumar@intel.com List-Id: intel-gfx@lists.freedesktop.org T24gVGh1LCAxNSBEZWMgMjAxNiwgTWFkaGF2IENoYXVoYW4gPG1hZGhhdi5jaGF1aGFuQGludGVs LmNvbT4gd3JvdGU6Cj4gRnJvbTogRGVlcGFrIE0gPG0uZGVlcGFrQGludGVsLmNvbT4KPgo+IHYy OiBBZGRyZXNzZWQgSmFuaSdzIFJldmlldyBjb21tZW50cyAocmVuYW1lZCBiaXQgZmllbGQgbWFj cm9zKQo+Cj4gU2lnbmVkLW9mZi1ieTogRGVlcGFrIE0gPG0uZGVlcGFrQGludGVsLmNvbT4KPiBT aWduZWQtb2ZmLWJ5OiBNYWRoYXYgQ2hhdWhhbiA8bWFkaGF2LmNoYXVoYW5AaW50ZWwuY29tPgoK UHVzaGVkIHRvIGRybS1pbnRlbC1uZXh0LXF1ZXVlZCwgdGhhbmtzIGZvciB0aGUgcGF0Y2guCgpC UiwKSmFuaS4KCgo+IC0tLQo+ICBkcml2ZXJzL2dwdS9kcm0vaTkxNS9pOTE1X3JlZy5oIHwgMTUg KysrKysrKysrKysrKysrCj4gIDEgZmlsZSBjaGFuZ2VkLCAxNSBpbnNlcnRpb25zKCspCj4KPiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2k5MTUvaTkxNV9yZWcuaCBiL2RyaXZlcnMvZ3B1 L2RybS9pOTE1L2k5MTVfcmVnLmgKPiBpbmRleCA5MDY4NWQyLi44ZTQ3YjU5IDEwMDY0NAo+IC0t LSBhL2RyaXZlcnMvZ3B1L2RybS9pOTE1L2k5MTVfcmVnLmgKPiArKysgYi9kcml2ZXJzL2dwdS9k cm0vaTkxNS9pOTE1X3JlZy5oCj4gQEAgLTg2NzIsNiArODY3MiwyMSBAQCBlbnVtIHsKPiAgI2Rl ZmluZSAgQlhUX1BJUEVfU0VMRUNUX1NISUZUCQkJCTcKPiAgI2RlZmluZSAgQlhUX1BJUEVfU0VM RUNUX01BU0sJCQkJKDcgPDwgNykKPiAgI2RlZmluZSAgQlhUX1BJUEVfU0VMRUNUKHBpcGUpCQkJ CSgocGlwZSkgPDwgNykKPiArI2RlZmluZSAgR0xLX1BIWV9TVEFUVVNfUE9SVF9SRUFEWQkJCSgx IDw8IDMxKSAvKiBSTyAqLwo+ICsjZGVmaW5lICBHTEtfVUxQU19OT1RfQUNUSVZFCQkJCSgxIDw8 IDMwKSAvKiBSTyAqLwo+ICsjZGVmaW5lICBHTEtfTUlQSUlPX1JFU0VUX1JFTEVBU0VECQkJKDEg PDwgMjgpCj4gKyNkZWZpbmUgIEdMS19DTE9DS19MQU5FX1NUT1BfU1RBVEUJCQkoMSA8PCAyNykg LyogUk8gKi8KPiArI2RlZmluZSAgR0xLX0RBVEFfTEFORV9TVE9QX1NUQVRFCQkJKDEgPDwgMjYp IC8qIFJPICovCj4gKyNkZWZpbmUgIEdMS19MUF9XQUtFCQkJCQkoMSA8PCAyMikKPiArI2RlZmlu ZSAgR0xLX0xQMTFfTE9XX1BXUl9NT0RFCQkJCSgxIDw8IDIxKQo+ICsjZGVmaW5lICBHTEtfTFAw MF9MT1dfUFdSX01PREUJCQkJKDEgPDwgMjApCj4gKyNkZWZpbmUgIEdMS19GSVJFV0FMTF9FTkFC TEUJCQkJKDEgPDwgMTYpCj4gKyNkZWZpbmUgIEJYVF9QSVhFTF9PVkVSTEFQX0NOVF9NQVNLCQkJ KDB4ZiA8PCAxMCkKPiArI2RlZmluZSAgQlhUX1BJWEVMX09WRVJMQVBfQ05UX1NISUZUCQkJMTAK PiArI2RlZmluZSAgQlhUX0RTQ19FTkFCTEUJCQkJCSgxIDw8IDMpCj4gKyNkZWZpbmUgIEJYVF9S R0JfRkxJUAkJCQkJKDEgPDwgMikKPiArI2RlZmluZSAgR0xLX01JUElJT19QT1JUX1BPV0VSRUQJ CQkoMSA8PCAxKSAvKiBSTyAqLwo+ICsjZGVmaW5lICBHTEtfTUlQSUlPX0VOQUJMRQkJCQkoMSA8 PCAwKQo+ICAKPiAgI2RlZmluZSBfTUlQSUFfREFUQV9BRERSRVNTCQkoZGV2X3ByaXYtPm1pcGlf bW1pb19iYXNlICsgMHhiMTA4KQo+ICAjZGVmaW5lIF9NSVBJQ19EQVRBX0FERFJFU1MJCShkZXZf cHJpdi0+bWlwaV9tbWlvX2Jhc2UgKyAweGI5MDgpCgotLSAKSmFuaSBOaWt1bGEsIEludGVsIE9w ZW4gU291cmNlIFRlY2hub2xvZ3kgQ2VudGVyCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2ludGVsLWdmeAo=