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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com>,
	drm-intel-fixes@lists.freedesktop.org
Subject: Re: [PATCH 2/2] agp/intel: Flush chipset writes after	updating a single PTE
Date: Thu, 18 Aug 2016 18:18:03 +0300	[thread overview]
Message-ID: <8737m2nm1g.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <20160818131258.20431-2-chris@chris-wilson.co.uk>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> After we update one PTE for a page, the caller expects to be able to
> immediately use that through a GGTT read/write. To comply with the
> callers expectations we therefore need to flush the chipset buffers
> before returning.
>
> Reported-by: Matti Hämäläinen <ccr@tnsp.org>
> Fixes: d6473f566417 ("drm/i915: Add support for mapping an object page...")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>

> Cc: Ankitprasad Sharma <ankitprasad.r.sharma@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Tested-by: Matti Hämäläinen <ccr@tnsp.org>
> Cc: drm-intel-fixes@lists.freedesktop.org
> ---
>  drivers/char/agp/intel-gtt.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 44311296ec02..0f7d28a98b9a 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -845,6 +845,8 @@ void intel_gtt_insert_page(dma_addr_t addr,
>  			   unsigned int flags)
>  {
>  	intel_private.driver->write_entry(addr, pg, flags);
> +	if (intel_private.driver->chipset_flush)
> +		intel_private.driver->chipset_flush();
>  }
>  EXPORT_SYMBOL(intel_gtt_insert_page);
>  
> -- 
> 2.9.3
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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  reply	other threads:[~2016-08-18 15:18 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-18 13:12 [PATCH 1/2] drm/i915: Unconditionally flush any chipset buffers before execbuf Chris Wilson
2016-08-18 13:12 ` [PATCH 2/2] agp/intel: Flush chipset writes after updating a single PTE Chris Wilson
2016-08-18 15:18   ` Mika Kuoppala [this message]
2016-08-18 13:33 ` [PATCH v2] drm/i915: Fallback to single page pwrite/pread if unable to release fence Chris Wilson
2016-08-18 13:52 ` ✓ Ro.CI.BAT: success for series starting with [1/2] drm/i915: Unconditionally flush any chipset buffers before execbuf Patchwork
2016-08-18 13:59 ` [PATCH 1/2] " Mika Kuoppala
2016-08-18 14:31   ` Chris Wilson
2016-08-18 14:18 ` ✗ Ro.CI.BAT: warning for series starting with [v2] drm/i915: Fallback to single page pwrite/pread if unable to release fence (rev2) Patchwork

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