From: Jani Nikula <jani.nikula@linux.intel.com>
To: Paulo Zanoni <przanoni@gmail.com>, intel-gfx@lists.freedesktop.org
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>, stable@vger.kernel.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: properly reenable gen8 pipe IRQs
Date: Wed, 08 Oct 2014 16:49:59 +0300 [thread overview]
Message-ID: <8738ay6588.fsf@intel.com> (raw)
In-Reply-To: <1412715772-1884-1-git-send-email-przanoni@gmail.com>
On Wed, 08 Oct 2014, Paulo Zanoni <przanoni@gmail.com> wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> We were missing the pipe B/C vblank bits! Take a look at
> gen8_de_irq_postinstall for a comparison.
>
> This should fix a bunch of IGT tests.
>
> There are a few more things we could improve on this code, but this
> should be the minimal fix to unblock us.
>
> v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville)
>
> Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640
> Testcase: igt/*
> Cc: stable@vger.kernel.org
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Pushed to drm-intel-next-fixes, thanks for the patch and review.
Paulo, please ask for retests on all relevant bug reports.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index b12c4c4..c141ff8 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev)
>
> void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv)
> {
> + uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> +
> spin_lock_irq(&dev_priv->irq_lock);
> GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B],
> - ~dev_priv->de_irq_mask[PIPE_B]);
> + ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
> GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C],
> - ~dev_priv->de_irq_mask[PIPE_C]);
> + ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
> spin_unlock_irq(&dev_priv->irq_lock);
> }
>
> --
> 2.1.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
prev parent reply other threads:[~2014-10-08 13:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-07 19:11 [PATCH 1/2] drm/i915: properly reenable gen8 pipe IRQs Paulo Zanoni
2014-10-07 19:11 ` [PATCH 2/2] drm/i915: only run hsw_power_well_post_enable when really needed Paulo Zanoni
2014-10-07 20:00 ` Ville Syrjälä
2014-10-22 18:34 ` Daniel Vetter
2014-10-07 19:58 ` [Intel-gfx] [PATCH 1/2] drm/i915: properly reenable gen8 pipe IRQs Ville Syrjälä
2014-10-07 20:36 ` Paulo Zanoni
2014-10-07 21:02 ` [PATCH] " Paulo Zanoni
2014-10-08 8:25 ` [Intel-gfx] " Jani Nikula
2014-10-08 18:36 ` Paulo Zanoni
2014-10-08 13:49 ` Jani Nikula [this message]
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