From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [Intel-gfx] [PATCH] drm/i915: properly reenable gen8 pipe IRQs Date: Wed, 08 Oct 2014 16:49:59 +0300 Message-ID: <8738ay6588.fsf@intel.com> References: <1412715772-1884-1-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: In-Reply-To: <1412715772-1884-1-git-send-email-przanoni@gmail.com> Sender: stable-owner@vger.kernel.org To: Paulo Zanoni , intel-gfx@lists.freedesktop.org Cc: Paulo Zanoni , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Wed, 08 Oct 2014, Paulo Zanoni wrote: > From: Paulo Zanoni > > We were missing the pipe B/C vblank bits! Take a look at > gen8_de_irq_postinstall for a comparison. > > This should fix a bunch of IGT tests. > > There are a few more things we could improve on this code, but this > should be the minimal fix to unblock us. > > v2: s/extra_iir/extra_ier/ because IIR doesn't make sense (Ville) > > Bugzilla:https://bugs.freedesktop.org/show_bug.cgi?id=83640 > Testcase: igt/* > Cc: stable@vger.kernel.org > Signed-off-by: Paulo Zanoni Pushed to drm-intel-next-fixes, thanks for the patch and review. Paulo, please ask for retests on all relevant bug reports. BR, Jani. > --- > drivers/gpu/drm/i915/i915_irq.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index b12c4c4..c141ff8 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3166,11 +3166,13 @@ static void gen8_irq_reset(struct drm_device *dev) > > void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv) > { > + uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN; > + > spin_lock_irq(&dev_priv->irq_lock); > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B, dev_priv->de_irq_mask[PIPE_B], > - ~dev_priv->de_irq_mask[PIPE_B]); > + ~dev_priv->de_irq_mask[PIPE_B] | extra_ier); > GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C, dev_priv->de_irq_mask[PIPE_C], > - ~dev_priv->de_irq_mask[PIPE_C]); > + ~dev_priv->de_irq_mask[PIPE_C] | extra_ier); > spin_unlock_irq(&dev_priv->irq_lock); > } > > -- > 2.1.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center