[Intel-gfx] [PATCH v5 0/7] Add MTL PMU support for multi-gt

Umesh Nerlige Ramappa
2023-05-16T23:35:41Z

With MTL, frequency and rc6 counters are specific to a gt. Export these
counters via gt-specific events to the user space.

v2: Remove aggregation support from kernel
v3: Review comments (Ashutosh, Tvrtko)
v4:
- Include R-b for 6/6
- Add Test-with
- Fix versioning info in cover letter
v5:
- Include "drm/i915/pmu: Change bitmask of enabled events to u32"

Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Test-with: 20230513022234.2832233-1-umesh.nerlige.ramappa@intel.com

Tvrtko Ursulin (7):
drm/i915/pmu: Change bitmask of enabled events to u32
drm/i915/pmu: Support PMU for all engines
drm/i915/pmu: Skip sampling engines with no enabled counters
drm/i915/pmu: Transform PMU parking code to be GT based
drm/i915/pmu: Add reference counting to the sampling timer
drm/i915/pmu: Prepare for multi-tile non-engine counters
drm/i915/pmu: Export counters from all tiles

drivers/gpu/drm/i915/gt/intel_gt_pm.c | 4 +-
drivers/gpu/drm/i915/i915_pmu.c | 292 ++++++++++++++++++--------
drivers/gpu/drm/i915/i915_pmu.h | 24 ++-
include/uapi/drm/i915_drm.h | 17 +-
4 files changed, 240 insertions(+), 97 deletions(-)

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2.36.1