From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F2E53ECAAD8 for ; Mon, 19 Sep 2022 03:14:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAC5210E4F7; Mon, 19 Sep 2022 03:14:18 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6B92710E4F7 for ; Mon, 19 Sep 2022 03:14:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663557256; x=1695093256; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=V3if0cdmPidMYLOuOjg6HW95xnTAakEzhFRTCX5DuCg=; b=Rp3RYqk2Wi6VlBeAIYQyBOshxNXw7ics6EzRdCeNY3HVE6YppNcwJONG NqRC0Oo+2093+7zk6TAUQGt0qdZU/u+MUx1GFqeH9bFlQMJY2Sg/EJSvq n0QtAHzyhZBLWnYO5eL5TotqKrzA2sDPnCFKf6Tp51FNIuGsrXIuaskVh KmceLNnDgnzUa9/yt+ZbMuwOWeKpao7oeho1BReq+mLkuDWy0GzQjI3CW EiYBh0wuqr3LZUPoiQucoEcP1Xohzft5lr6st6gPYlZbs/7SghES9MrvQ WK89/u131wxGp0RLh7+ifiKelgfPGGbCv0xxy2Ns3Nk1BZFci7Owav1v7 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10474"; a="279023915" X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="279023915" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 20:14:15 -0700 X-IronPort-AV: E=Sophos;i="5.93,325,1654585200"; d="scan'208";a="620695769" Received: from vparekh-mobl1.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.255.228.222]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Sep 2022 20:14:15 -0700 Date: Sun, 18 Sep 2022 20:14:14 -0700 Message-ID: <874jx4hx89.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: intel-gfx@lists.freedesktop.org In-Reply-To: <20220917031501.1916123-1-ashutosh.dixit@intel.com> References: <20220917031501.1916123-1-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH] drm/i915/debugfs: Fix perf_limit_reasons debugfs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Fri, 16 Sep 2022 20:15:01 -0700, Ashutosh Dixit wrote: > > Register GT0_PERF_LIMIT_REASONS (0x1381a8) is available only for Gen11+. PLEASE IGNORE THIS PATCH. I will submit a different patch for this issue. Thanks. -- Ashutosh > On Gen < 5 igt@debugfs_test@read_all_entries results in the following oops: > > <1> [88.829420] BUG: unable to handle page fault for address: ffffc90000bb81a8 > <1> [88.829438] #PF: supervisor read access in kernel mode > <1> [88.829447] #PF: error_code(0x0000) - not-present page > > Bspec: 20008 > Fixes: fe5979665f64 ("drm/i915/debugfs: Add perf_limit_reasons in debugfs") > Signed-off-by: Ashutosh Dixit > --- > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > index 68310881a793..e7f057821cd0 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > @@ -660,6 +660,9 @@ static int perf_limit_reasons_get(void *data, u64 *val) > struct intel_gt *gt = data; > intel_wakeref_t wakeref; > > + if (GRAPHICS_VER(gt->i915) < 11) > + return 0; > + > with_intel_runtime_pm(gt->uncore->rpm, wakeref) > *val = intel_uncore_read(gt->uncore, intel_gt_perf_limit_reasons_reg(gt)); > > @@ -671,6 +674,9 @@ static int perf_limit_reasons_clear(void *data, u64 val) > struct intel_gt *gt = data; > intel_wakeref_t wakeref; > > + if (GRAPHICS_VER(gt->i915) < 11) > + return 0; > + > /* > * Clear the upper 16 "log" bits, the lower 16 "status" bits are > * read-only. The upper 16 "log" bits are identical to the lower 16 > -- > 2.34.1 >