From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 26DB2C54EE9 for ; Fri, 16 Sep 2022 05:40:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EE9E710E3B4; Fri, 16 Sep 2022 05:40:12 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4992A10E3B4 for ; Fri, 16 Sep 2022 05:40:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663306809; x=1694842809; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=372xbBLYrx50FmAzYUNISyQnXqovUeVaK67KsKfpTks=; b=QmvpNLddipicbpEXDA8R4PXMQ5/HxfGVFuBfbD58CzDe6Wc87ydG6Iij Ui8xyxHk4q9toocMK69uJNDbKCXHjARyjeu8UIwAOygmQL528b/YiY7JA mRJ4MQC63C6K1vYsWomJOatzWMEYwMYT+E/ddMRdTcVb+rit1EhyIpFmP x2sAb6bUtpiUEgSIIgz/M0k2rQZXPX2YSy7JRO3ygy3B5ye7KyyCxOoIn 0KK8A1WwrzgKW02CXLFvTcxPoIPrIzc30J5fjqI9QXyQ3uBsi2bn5o2iU BDBSj4tj+Ct8anBgzRM0fxpY5phe+QHjTzxtw3e3f1lpYi2q8MBMaaDfm w==; X-IronPort-AV: E=McAfee;i="6500,9779,10471"; a="279298598" X-IronPort-AV: E=Sophos;i="5.93,319,1654585200"; d="scan'208";a="279298598" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2022 22:40:08 -0700 X-IronPort-AV: E=Sophos;i="5.93,319,1654585200"; d="scan'208";a="648132811" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.209.41.22]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2022 22:40:07 -0700 Date: Thu, 15 Sep 2022 22:40:07 -0700 Message-ID: <874jx7513c.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20220823204155.8178-18-umesh.nerlige.ramappa@intel.com> References: <20220823204155.8178-1-umesh.nerlige.ramappa@intel.com> <20220823204155.8178-18-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 17/19] drm/i915/perf: Save/restore EU flex counters across reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 23 Aug 2022 13:41:53 -0700, Umesh Nerlige Ramappa wrote: > > If a drm client is killed, then hw contexts used by the client are reset > immediately. This reset clears the EU flex counter configuration. If an > OA use case is running in parallel, it would start seeing zeroed eu > counter values following the reset even if the drm client is restarted. > Save/restore the EU flex counter config so that the EU counters can be > monitored continuously across resets. Reviewed-by: Ashutosh Dixit Not sure if this needs to be done for non-GuC (execlists) too? Anyway that's a later patch. > Signed-off-by: Umesh Nerlige Ramappa > --- > drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > index 74cbe8eaf531..3e152219fcb2 100644 > --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c > @@ -375,6 +375,14 @@ static int guc_mmio_regset_init(struct temp_regset *regset, > for (i = 0; i < GEN9_LNCFCMOCS_REG_COUNT; i++) > ret |= GUC_MMIO_REG_ADD(gt, regset, GEN9_LNCFCMOCS(i), false); > > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL0, false); > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL1, false); > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL2, false); > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL3, false); > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL4, false); > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL5, false); > + ret |= GUC_MMIO_REG_ADD(gt, regset, EU_PERF_CNTL6, false); > + > return ret ? -1 : 0; > } > > -- > 2.25.1 >