From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 62D7DC433F5 for ; Mon, 16 May 2022 12:29:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A251410E80B; Mon, 16 May 2022 12:29:11 +0000 (UTC) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4F3BB10EA8A for ; Mon, 16 May 2022 12:29:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652704150; x=1684240150; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=YcEyXMV/MNhGDgX7wMsPtvkJzCQJp1Xdt5z3CEoGXSQ=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 03 May 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Deduplicate the crtc_ timigns comparisons. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++------------ > 1 file changed, 18 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/d= rm/i915/display/intel_display.c > index 7d488d320762..e38d93beafdd 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -6073,6 +6073,21 @@ intel_pipe_config_compare(const struct intel_crtc_= state *current_config, > } \ > } while (0) >=20=20 > +#define PIPE_CONF_CHECK_TIMINGS(name) do { \ > + PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ > + PIPE_CONF_CHECK_I(name.crtc_htotal); \ > + PIPE_CONF_CHECK_I(name.crtc_hblank_start); \ > + PIPE_CONF_CHECK_I(name.crtc_hblank_end); \ > + PIPE_CONF_CHECK_I(name.crtc_hsync_start); \ > + PIPE_CONF_CHECK_I(name.crtc_hsync_end); \ > + PIPE_CONF_CHECK_I(name.crtc_vdisplay); \ > + PIPE_CONF_CHECK_I(name.crtc_vtotal); \ > + PIPE_CONF_CHECK_I(name.crtc_vblank_start); \ > + PIPE_CONF_CHECK_I(name.crtc_vblank_end); \ > + PIPE_CONF_CHECK_I(name.crtc_vsync_start); \ > + PIPE_CONF_CHECK_I(name.crtc_vsync_end); \ > +} while (0) > + > /* This is required for BDW+ where there is only one set of registers for > * switching between high and low RR. > * This macro can be used whenever a comparison has to be made between o= ne > @@ -6190,33 +6205,8 @@ intel_pipe_config_compare(const struct intel_crtc_= state *current_config, > PIPE_CONF_CHECK_I(framestart_delay); > PIPE_CONF_CHECK_I(msa_timing_delay); >=20=20 > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end); > - > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start); > - PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end); > - > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end); > - > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start); > - PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end); > + PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode); > + PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode); >=20=20 > PIPE_CONF_CHECK_I(pixel_multiplier); >=20=20 > @@ -6392,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_s= tate *current_config, > #undef PIPE_CONF_CHECK_FLAGS > #undef PIPE_CONF_CHECK_CLOCK_FUZZY > #undef PIPE_CONF_CHECK_COLOR_LUT > +#undef PIPE_CONF_CHECK_TIMINGS > #undef PIPE_CONF_QUIRK >=20=20 > return ret; --=20 Jani Nikula, Intel Open Source Graphics Center