* [Intel-gfx] [RFC 0/2] Compile out integrated
@ 2022-02-01 11:15 Tvrtko Ursulin
2022-02-01 11:15 ` [Intel-gfx] [RFC 1/2] igp kconfig Tvrtko Ursulin
` (7 more replies)
0 siblings, 8 replies; 19+ messages in thread
From: Tvrtko Ursulin @ 2022-02-01 11:15 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula, Michael Cheng, Lucas De Marchi
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Quicky and dirty hack based on some old ideas. Thought maybe the approach might
interest the Arm port guys. But with IS_GEN_RANGE removed easy gains are not so
big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I haven't looked
into that side.
3884664 449681 6720 4341065 423d49 i915.ko.tip
3599989 429034 6688 4035711 3d947f i915.ko.noigp
Note debug kconfig so everything is inflated. Whether or not the relative gain
would change with production kconfig I am not sure.
P.S.
I was a bit curious there were no build errors around functions no longer used
so either there were none (would mean patch is not really that effective), or
something changed with compiler warnings/smarts. Haven't looked into it.
Tvrtko Ursulin (2):
igp kconfig
jsl/ehl
drivers/gpu/drm/i915/Kconfig | 5 +
drivers/gpu/drm/i915/Kconfig.platforms | 7 +
.../drm/i915/display/intel_ddi_buf_trans.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 128 +++++++++++-------
drivers/gpu/drm/i915/i915_pci.c | 44 +++++-
6 files changed, 134 insertions(+), 56 deletions(-)
create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms
--
2.32.0
^ permalink raw reply [flat|nested] 19+ messages in thread* [Intel-gfx] [RFC 1/2] igp kconfig 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin @ 2022-02-01 11:15 ` Tvrtko Ursulin 2022-02-01 11:15 ` [Intel-gfx] [RFC 2/2] jsl/ehl Tvrtko Ursulin ` (6 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Tvrtko Ursulin @ 2022-02-01 11:15 UTC (permalink / raw) To: Intel-gfx; +Cc: Jani Nikula, Michael Cheng, Lucas De Marchi From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/Kconfig | 5 + drivers/gpu/drm/i915/Kconfig.platforms | 7 ++ drivers/gpu/drm/i915/i915_drv.h | 126 +++++++++++++++---------- drivers/gpu/drm/i915/i915_pci.c | 44 ++++++++- 4 files changed, 129 insertions(+), 53 deletions(-) create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 2ac220bfd0ed..e8c2549ca433 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -145,6 +145,11 @@ config DRM_I915_PXP protected session and manage the status of the alive software session, as well as its life cycle. +menu "Platform support" +depends on DRM_I915 +source "drivers/gpu/drm/i915/Kconfig.platforms" +endmenu + menu "drm/i915 Debugging" depends on DRM_I915 depends on EXPERT diff --git a/drivers/gpu/drm/i915/Kconfig.platforms b/drivers/gpu/drm/i915/Kconfig.platforms new file mode 100644 index 000000000000..731be430cfad --- /dev/null +++ b/drivers/gpu/drm/i915/Kconfig.platforms @@ -0,0 +1,7 @@ +config DRM_I915_INTEGRATED_GPU_SUPPORT + bool "Support integrated GPUs" + default y + depends on DRM_I915 + help + Include support for integrated GPUs. + diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 00e7594b59c9..1d22d72163c1 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1118,8 +1118,26 @@ static inline struct intel_gt *to_gt(struct drm_i915_private *i915) #define GRAPHICS_VER(i915) (INTEL_INFO(i915)->graphics.ver) #define GRAPHICS_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->graphics.ver, \ INTEL_INFO(i915)->graphics.rel) + +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT #define IS_GRAPHICS_VER(i915, from, until) \ (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until)) +#else +#define IS_GRAPHICS_VER(i915, from, until) \ +({ \ + const unsigned int s_ = 12; \ + const unsigned int e_ = UINT_MAX; \ + unsigned int res_; \ + \ + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ + res_ = GRAPHICS_VER(i915) >= (from) && \ + GRAPHICS_VER(i915) <= (until); \ + else \ + res_ = 0; \ + \ + (res_); \ +}) +#endif #define MEDIA_VER(i915) (INTEL_INFO(i915)->media.ver) #define MEDIA_VER_FULL(i915) IP_VER(INTEL_INFO(i915)->media.arch, \ @@ -1213,49 +1231,53 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb); } +#define IS_IGP_PLATFORM(dev_priv, p) \ + (IS_ENABLED(CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT) && \ + IS_PLATFORM(dev_priv, p)) + #define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile) #define IS_DGFX(dev_priv) (INTEL_INFO(dev_priv)->is_dgfx) -#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) -#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) -#define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) -#define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) -#define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) -#define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) -#define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) -#define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) -#define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) -#define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) -#define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) -#define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) +#define IS_I830(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I830) +#define IS_I845G(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I845G) +#define IS_I85X(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I85X) +#define IS_I865G(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I865G) +#define IS_I915G(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I915G) +#define IS_I915GM(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I915GM) +#define IS_I945G(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I945G) +#define IS_I945GM(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I945GM) +#define IS_I965G(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I965G) +#define IS_I965GM(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_I965GM) +#define IS_G45(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_G45) +#define IS_GM45(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_GM45) #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) -#define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) +#define IS_PINEVIEW(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_PINEVIEW) +#define IS_G33(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_G33) +#define IS_IRONLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_IRONLAKE) #define IS_IRONLAKE_M(dev_priv) \ - (IS_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) -#define IS_SANDYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) -#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) + (IS_IGP_PLATFORM(dev_priv, INTEL_IRONLAKE) && IS_MOBILE(dev_priv)) +#define IS_SANDYBRIDGE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_SANDYBRIDGE) +#define IS_IVYBRIDGE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_IVYBRIDGE) #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 1) -#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) -#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) -#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) -#define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) -#define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) -#define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) -#define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) -#define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) -#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) -#define IS_COMETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COMETLAKE) -#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) -#define IS_JSL_EHL(dev_priv) (IS_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ - IS_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) -#define IS_TIGERLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_TIGERLAKE) -#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE) +#define IS_VALLEYVIEW(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_VALLEYVIEW) +#define IS_CHERRYVIEW(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_CHERRYVIEW) +#define IS_HASWELL(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_HASWELL) +#define IS_BROADWELL(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_BROADWELL) +#define IS_SKYLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_SKYLAKE) +#define IS_BROXTON(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_BROXTON) +#define IS_KABYLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_KABYLAKE) +#define IS_GEMINILAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_GEMINILAKE) +#define IS_COFFEELAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_COFFEELAKE) +#define IS_COMETLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_COMETLAKE) +#define IS_ICELAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ICELAKE) +#define IS_JSL_EHL(dev_priv) (IS_IGP_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ + IS_IGP_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) +#define IS_TIGERLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_TIGERLAKE) +#define IS_ROCKETLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ROCKETLAKE) #define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1) -#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) -#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) +#define IS_ALDERLAKE_S(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ALDERLAKE_S) +#define IS_ALDERLAKE_P(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ALDERLAKE_P) #define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV) #define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2) #define IS_DG2_G10(dev_priv) \ @@ -1263,34 +1285,34 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_DG2_G11(dev_priv) \ IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11) #define IS_ADLS_RPLS(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S) + (IS_ALDERLAKE_S(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)) #define IS_ADLP_N(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N) + (IS_ALDERLAKE_P(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)) #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) #define IS_BDW_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT) + (IS_BROADWELL(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)) #define IS_BDW_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX) + (IS_BROADWELL(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)) #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 3) #define IS_HSW_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT) + (IS_HASWELL(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)) #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 3) #define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 1) /* ULX machines are also considered ULT. */ #define IS_HSW_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX) + (IS_HASWELL(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)) #define IS_SKL_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT) + (IS_SKYLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)) #define IS_SKL_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX) + (IS_SKYLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)) #define IS_KBL_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT) + (IS_KABYLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)) #define IS_KBL_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX) + (IS_KABYLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)) #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 2) #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ @@ -1302,29 +1324,29 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 3) #define IS_CFL_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT) + (IS_COFFEELAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)) #define IS_CFL_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX) + (IS_COFFEELAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)) #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 2) #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 3) #define IS_CML_ULT(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT) + (IS_COMETLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)) #define IS_CML_ULX(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX) + (IS_COMETLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)) #define IS_CML_GT2(dev_priv) (IS_COMETLAKE(dev_priv) && \ INTEL_INFO(dev_priv)->gt == 2) #define IS_ICL_WITH_PORT_F(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF) + (IS_ICELAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)) #define IS_TGL_U(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT) + (IS_TIGERLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULT)) #define IS_TGL_Y(dev_priv) \ - IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX) + (IS_TIGERLAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_ULX)) #define IS_SKL_GRAPHICS_STEP(p, since, until) (IS_SKYLAKE(p) && IS_GRAPHICS_STEP(p, since, until)) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 983546d5f415..2797cc369835 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -201,6 +201,7 @@ GEN_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info i830_info = { I830_FEATURES, PLATFORM(INTEL_I830), @@ -222,6 +223,7 @@ static const struct intel_device_info i865g_info = { PLATFORM(INTEL_I865G), .display.fbc_mask = BIT(INTEL_FBC_A), }; +#endif #define GEN3_FEATURES \ GEN(3), \ @@ -239,6 +241,7 @@ static const struct intel_device_info i865g_info = { GEN_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info i915g_info = { GEN3_FEATURES, PLATFORM(INTEL_I915G), @@ -312,6 +315,7 @@ static const struct intel_device_info pnv_m_info = { .display.has_overlay = 1, .dma_mask_size = 36, }; +#endif #define GEN4_FEATURES \ GEN(4), \ @@ -330,6 +334,7 @@ static const struct intel_device_info pnv_m_info = { GEN_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info i965g_info = { GEN4_FEATURES, PLATFORM(INTEL_I965G), @@ -365,6 +370,7 @@ static const struct intel_device_info gm45_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0), .gpu_reset_clobbers_display = false, }; +#endif #define GEN5_FEATURES \ GEN(5), \ @@ -383,6 +389,7 @@ static const struct intel_device_info gm45_info = { GEN_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info ilk_d_info = { GEN5_FEATURES, PLATFORM(INTEL_IRONLAKE), @@ -395,6 +402,7 @@ static const struct intel_device_info ilk_m_info = { .has_rps = true, .display.fbc_mask = BIT(INTEL_FBC_A), }; +#endif #define GEN6_FEATURES \ GEN(6), \ @@ -421,6 +429,7 @@ static const struct intel_device_info ilk_m_info = { GEN6_FEATURES, \ PLATFORM(INTEL_SANDYBRIDGE) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info snb_d_gt1_info = { SNB_D_PLATFORM, .gt = 1, @@ -430,6 +439,7 @@ static const struct intel_device_info snb_d_gt2_info = { SNB_D_PLATFORM, .gt = 2, }; +#endif #define SNB_M_PLATFORM \ GEN6_FEATURES, \ @@ -437,6 +447,7 @@ static const struct intel_device_info snb_d_gt2_info = { .is_mobile = 1 +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info snb_m_gt1_info = { SNB_M_PLATFORM, .gt = 1, @@ -446,6 +457,7 @@ static const struct intel_device_info snb_m_gt2_info = { SNB_M_PLATFORM, .gt = 2, }; +#endif #define GEN7_FEATURES \ GEN(7), \ @@ -474,6 +486,7 @@ static const struct intel_device_info snb_m_gt2_info = { PLATFORM(INTEL_IVYBRIDGE), \ .has_l3_dpf = 1 +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info ivb_d_gt1_info = { IVB_D_PLATFORM, .gt = 1, @@ -483,6 +496,7 @@ static const struct intel_device_info ivb_d_gt2_info = { IVB_D_PLATFORM, .gt = 2, }; +#endif #define IVB_M_PLATFORM \ GEN7_FEATURES, \ @@ -490,6 +504,7 @@ static const struct intel_device_info ivb_d_gt2_info = { .is_mobile = 1, \ .has_l3_dpf = 1 +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info ivb_m_gt1_info = { IVB_M_PLATFORM, .gt = 1, @@ -534,6 +549,7 @@ static const struct intel_device_info vlv_info = { GEN_DEFAULT_PAGE_SIZES, GEN_DEFAULT_REGIONS, }; +#endif #define G75_FEATURES \ GEN7_FEATURES, \ @@ -552,6 +568,7 @@ static const struct intel_device_info vlv_info = { PLATFORM(INTEL_HASWELL), \ .has_l3_dpf = 1 +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info hsw_gt1_info = { HSW_PLATFORM, .gt = 1, @@ -566,6 +583,7 @@ static const struct intel_device_info hsw_gt3_info = { HSW_PLATFORM, .gt = 3, }; +#endif #define GEN8_FEATURES \ G75_FEATURES, \ @@ -580,6 +598,7 @@ static const struct intel_device_info hsw_gt3_info = { GEN8_FEATURES, \ PLATFORM(INTEL_BROADWELL) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info bdw_gt1_info = { BDW_PLATFORM, .gt = 1, @@ -632,6 +651,7 @@ static const struct intel_device_info chv_info = { GEN_DEFAULT_PAGE_SIZES, GEN_DEFAULT_REGIONS, }; +#endif #define GEN9_DEFAULT_PAGE_SIZES \ .page_sizes = I915_GTT_PAGE_SIZE_4K | \ @@ -654,6 +674,7 @@ static const struct intel_device_info chv_info = { GEN9_FEATURES, \ PLATFORM(INTEL_SKYLAKE) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info skl_gt1_info = { SKL_PLATFORM, .gt = 1, @@ -663,6 +684,7 @@ static const struct intel_device_info skl_gt2_info = { SKL_PLATFORM, .gt = 2, }; +#endif #define SKL_GT3_PLUS_PLATFORM \ SKL_PLATFORM, \ @@ -670,6 +692,7 @@ static const struct intel_device_info skl_gt2_info = { BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info skl_gt3_info = { SKL_GT3_PLUS_PLATFORM, .gt = 3, @@ -679,6 +702,7 @@ static const struct intel_device_info skl_gt4_info = { SKL_GT3_PLUS_PLATFORM, .gt = 4, }; +#endif #define GEN9_LP_FEATURES \ GEN(9), \ @@ -717,6 +741,7 @@ static const struct intel_device_info skl_gt4_info = { GEN9_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info bxt_info = { GEN9_LP_FEATURES, PLATFORM(INTEL_BROXTON), @@ -730,11 +755,13 @@ static const struct intel_device_info glk_info = { .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ GLK_COLORS, }; +#endif #define KBL_PLATFORM \ GEN9_FEATURES, \ PLATFORM(INTEL_KABYLAKE) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info kbl_gt1_info = { KBL_PLATFORM, .gt = 1, @@ -751,11 +778,13 @@ static const struct intel_device_info kbl_gt3_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; +#endif #define CFL_PLATFORM \ GEN9_FEATURES, \ PLATFORM(INTEL_COFFEELAKE) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info cfl_gt1_info = { CFL_PLATFORM, .gt = 1, @@ -772,11 +801,13 @@ static const struct intel_device_info cfl_gt3_info = { .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1), }; +#endif #define CML_PLATFORM \ GEN9_FEATURES, \ PLATFORM(INTEL_COMETLAKE) +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info cml_gt1_info = { CML_PLATFORM, .gt = 1, @@ -786,6 +817,7 @@ static const struct intel_device_info cml_gt2_info = { CML_PLATFORM, .gt = 2, }; +#endif #define GEN11_DEFAULT_PAGE_SIZES \ .page_sizes = I915_GTT_PAGE_SIZE_4K | \ @@ -823,6 +855,7 @@ static const struct intel_device_info cml_gt2_info = { .has_coherent_ggtt = false, \ .has_logical_ring_elsq = 1 +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info icl_info = { GEN11_FEATURES, PLATFORM(INTEL_ICELAKE), @@ -843,6 +876,7 @@ static const struct intel_device_info jsl_info = { .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0), .ppgtt_size = 36, }; +#endif #define GEN12_FEATURES \ GEN11_FEATURES, \ @@ -873,6 +907,7 @@ static const struct intel_device_info jsl_info = { .has_pxp = 1, \ .display.has_dsb = 0 /* FIXME: LUT load is broken with DSB */ +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info tgl_info = { GEN12_FEATURES, PLATFORM(INTEL_TIGERLAKE), @@ -893,6 +928,7 @@ static const struct intel_device_info rkl_info = { .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0), }; +#endif #define DGFX_FEATURES \ .memory_regions = REGION_SMEM | REGION_LMEM | REGION_STOLEN_LMEM, \ @@ -915,6 +951,7 @@ static const struct intel_device_info dg1_info = { .ppgtt_size = 47, }; +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info adl_s_info = { GEN12_FEATURES, PLATFORM(INTEL_ALDERLAKE_S), @@ -925,6 +962,7 @@ static const struct intel_device_info adl_s_info = { BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), .dma_mask_size = 39, }; +#endif #define XE_LPD_CURSOR_OFFSETS \ .cursor_offsets = { \ @@ -974,6 +1012,7 @@ static const struct intel_device_info adl_s_info = { }, \ XE_LPD_CURSOR_OFFSETS +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT static const struct intel_device_info adl_p_info = { GEN12_FEATURES, XE_LPD_FEATURES, @@ -989,6 +1028,7 @@ static const struct intel_device_info adl_p_info = { .ppgtt_size = 48, .dma_mask_size = 39, }; +#endif #undef GEN @@ -1065,6 +1105,7 @@ static const struct intel_device_info dg2_info = { * PCI ID matches, otherwise we'll use the wrong info struct above. */ static const struct pci_device_id pciidlist[] = { +#ifdef CONFIG_DRM_I915_INTEGRATED_GPU_SUPPORT INTEL_I830_IDS(&i830_info), INTEL_I845G_IDS(&i845g_info), INTEL_I85X_IDS(&i85x_info), @@ -1133,8 +1174,9 @@ static const struct pci_device_id pciidlist[] = { INTEL_ADLS_IDS(&adl_s_info), INTEL_ADLP_IDS(&adl_p_info), INTEL_ADLN_IDS(&adl_p_info), - INTEL_DG1_IDS(&dg1_info), INTEL_RPLS_IDS(&adl_s_info), +#endif + INTEL_DG1_IDS(&dg1_info), {0, 0, 0} }; MODULE_DEVICE_TABLE(pci, pciidlist); -- 2.32.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Intel-gfx] [RFC 2/2] jsl/ehl 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin 2022-02-01 11:15 ` [Intel-gfx] [RFC 1/2] igp kconfig Tvrtko Ursulin @ 2022-02-01 11:15 ` Tvrtko Ursulin 2022-02-01 11:26 ` Jani Nikula 2022-02-01 13:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Compile out integrated Patchwork ` (5 subsequent siblings) 7 siblings, 1 reply; 19+ messages in thread From: Tvrtko Ursulin @ 2022-02-01 11:15 UTC (permalink / raw) To: Intel-gfx; +Cc: Jani Nikula, Michael Cheng, Lucas De Marchi From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 2 ++ 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c index 0c32210bf503..37b48f7ab4fd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c @@ -1621,9 +1621,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) else encoder->get_buf_trans = tgl_get_dkl_buf_trans; } else if (DISPLAY_VER(i915) == 11) { - if (IS_PLATFORM(i915, INTEL_JASPERLAKE)) + if (IS_JASPERLAKE(i915)) encoder->get_buf_trans = jsl_get_combo_buf_trans; - else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) + else if (IS_ELKHARTLAKE(i915)) encoder->get_buf_trans = ehl_get_combo_buf_trans; else if (intel_phy_is_combo(i915, phy)) encoder->get_buf_trans = icl_get_combo_buf_trans; diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c index 6723c3de5a80..0d9b970c453f 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c @@ -2443,7 +2443,7 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params, static bool ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) { - return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && + return ((IS_ELKHARTLAKE(i915) && IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) && i915->dpll.ref_clks.nssc == 38400; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1d22d72163c1..241acd884135 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1271,6 +1271,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_COFFEELAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_COFFEELAKE) #define IS_COMETLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_COMETLAKE) #define IS_ICELAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ICELAKE) +#define IS_JASPERLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_JASPERLAKE) +#define IS_ELKHARTLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) #define IS_JSL_EHL(dev_priv) (IS_IGP_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ IS_IGP_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) #define IS_TIGERLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_TIGERLAKE) -- 2.32.0 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 2/2] jsl/ehl 2022-02-01 11:15 ` [Intel-gfx] [RFC 2/2] jsl/ehl Tvrtko Ursulin @ 2022-02-01 11:26 ` Jani Nikula 0 siblings, 0 replies; 19+ messages in thread From: Jani Nikula @ 2022-02-01 11:26 UTC (permalink / raw) To: Tvrtko Ursulin, Intel-gfx; +Cc: Michael Cheng, Lucas De Marchi On Tue, 01 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Should be split out and posted independently. Maybe we should consider s/IS_PLATFORM/__IS_PLATFORM/g too. BR, Jani. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c | 4 ++-- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 2 ++ > 3 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > index 0c32210bf503..37b48f7ab4fd 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c > @@ -1621,9 +1621,9 @@ void intel_ddi_buf_trans_init(struct intel_encoder *encoder) > else > encoder->get_buf_trans = tgl_get_dkl_buf_trans; > } else if (DISPLAY_VER(i915) == 11) { > - if (IS_PLATFORM(i915, INTEL_JASPERLAKE)) > + if (IS_JASPERLAKE(i915)) > encoder->get_buf_trans = jsl_get_combo_buf_trans; > - else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE)) > + else if (IS_ELKHARTLAKE(i915)) > encoder->get_buf_trans = ehl_get_combo_buf_trans; > else if (intel_phy_is_combo(i915, phy)) > encoder->get_buf_trans = icl_get_combo_buf_trans; > diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > index 6723c3de5a80..0d9b970c453f 100644 > --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c > @@ -2443,7 +2443,7 @@ static void icl_wrpll_params_populate(struct skl_wrpll_params *params, > static bool > ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915) > { > - return ((IS_PLATFORM(i915, INTEL_ELKHARTLAKE) && > + return ((IS_ELKHARTLAKE(i915) && > IS_JSL_EHL_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) || > IS_TIGERLAKE(i915) || IS_ALDERLAKE_P(i915)) && > i915->dpll.ref_clks.nssc == 38400; > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1d22d72163c1..241acd884135 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1271,6 +1271,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > #define IS_COFFEELAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_COFFEELAKE) > #define IS_COMETLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_COMETLAKE) > #define IS_ICELAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ICELAKE) > +#define IS_JASPERLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_JASPERLAKE) > +#define IS_ELKHARTLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_ELKHARTLAKE) > #define IS_JSL_EHL(dev_priv) (IS_IGP_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ > IS_IGP_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) > #define IS_TIGERLAKE(dev_priv) IS_IGP_PLATFORM(dev_priv, INTEL_TIGERLAKE) -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Compile out integrated 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin 2022-02-01 11:15 ` [Intel-gfx] [RFC 1/2] igp kconfig Tvrtko Ursulin 2022-02-01 11:15 ` [Intel-gfx] [RFC 2/2] jsl/ehl Tvrtko Ursulin @ 2022-02-01 13:17 ` Patchwork 2022-02-01 13:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork ` (4 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2022-02-01 13:17 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: Compile out integrated URL : https://patchwork.freedesktop.org/series/99570/ State : warning == Summary == $ dim checkpatch origin/drm-tip 15e05554122b igp kconfig -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one -:18: WARNING:EMBEDDED_FILENAME: It's generally not useful to have the filename in the file #18: FILE: drivers/gpu/drm/i915/Kconfig:150: +source "drivers/gpu/drm/i915/Kconfig.platforms" -:25: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #25: new file mode 100644 -:30: WARNING:CONFIG_DESCRIPTION: please write a help paragraph that fully describes the config symbol #30: FILE: drivers/gpu/drm/i915/Kconfig.platforms:1: +config DRM_I915_INTEGRATED_GPU_SUPPORT + bool "Support integrated GPUs" + default y + depends on DRM_I915 + help + Include support for integrated GPUs. + -:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i915' - possible side-effects? #50: FILE: drivers/gpu/drm/i915/i915_drv.h:1126: +#define IS_GRAPHICS_VER(i915, from, until) \ +({ \ + const unsigned int s_ = 12; \ + const unsigned int e_ = UINT_MAX; \ + unsigned int res_; \ + \ + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ + res_ = GRAPHICS_VER(i915) >= (from) && \ + GRAPHICS_VER(i915) <= (until); \ + else \ + res_ = 0; \ + \ + (res_); \ +}) -:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'from' - possible side-effects? #50: FILE: drivers/gpu/drm/i915/i915_drv.h:1126: +#define IS_GRAPHICS_VER(i915, from, until) \ +({ \ + const unsigned int s_ = 12; \ + const unsigned int e_ = UINT_MAX; \ + unsigned int res_; \ + \ + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ + res_ = GRAPHICS_VER(i915) >= (from) && \ + GRAPHICS_VER(i915) <= (until); \ + else \ + res_ = 0; \ + \ + (res_); \ +}) -:50: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'until' - possible side-effects? #50: FILE: drivers/gpu/drm/i915/i915_drv.h:1126: +#define IS_GRAPHICS_VER(i915, from, until) \ +({ \ + const unsigned int s_ = 12; \ + const unsigned int e_ = UINT_MAX; \ + unsigned int res_; \ + \ + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ + res_ = GRAPHICS_VER(i915) >= (from) && \ + GRAPHICS_VER(i915) <= (until); \ + else \ + res_ = 0; \ + \ + (res_); \ +}) -:55: WARNING:LEADING_SPACE: please, no spaces at the start of a line #55: FILE: drivers/gpu/drm/i915/i915_drv.h:1131: + \$ -:56: ERROR:SPACING: spaces required around that ':' (ctx:VxW) #56: FILE: drivers/gpu/drm/i915/i915_drv.h:1132: + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ ^ -:56: ERROR:SPACING: spaces required around that '?' (ctx:VxW) #56: FILE: drivers/gpu/drm/i915/i915_drv.h:1132: + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ ^ -:56: ERROR:SPACING: spaces required around that ':' (ctx:VxW) #56: FILE: drivers/gpu/drm/i915/i915_drv.h:1132: + if ((s_ > (from) ? (s_): (from)) <= ((e_) < (until)? (e_): (until))) \ ^ -:61: WARNING:LEADING_SPACE: please, no spaces at the start of a line #61: FILE: drivers/gpu/drm/i915/i915_drv.h:1137: + \$ -:145: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects? #145: FILE: drivers/gpu/drm/i915/i915_drv.h:1274: +#define IS_JSL_EHL(dev_priv) (IS_IGP_PLATFORM(dev_priv, INTEL_JASPERLAKE) || \ + IS_IGP_PLATFORM(dev_priv, INTEL_ELKHARTLAKE)) -:162: WARNING:LONG_LINE: line length of 106 exceeds 100 columns #162: FILE: drivers/gpu/drm/i915/i915_drv.h:1288: + (IS_ALDERLAKE_S(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL_S)) -:165: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #165: FILE: drivers/gpu/drm/i915/i915_drv.h:1290: + (IS_ALDERLAKE_P(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)) -:207: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #207: FILE: drivers/gpu/drm/i915/i915_drv.h:1327: + (IS_COFFEELAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)) -:210: WARNING:LONG_LINE: line length of 102 exceeds 100 columns #210: FILE: drivers/gpu/drm/i915/i915_drv.h:1329: + (IS_COFFEELAKE(dev_priv) && IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)) total: 3 errors, 10 warnings, 4 checks, 506 lines checked 528a41163c0e jsl/ehl -:7: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one total: 0 errors, 1 warnings, 0 checks, 27 lines checked ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Compile out integrated 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin ` (2 preceding siblings ...) 2022-02-01 13:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Compile out integrated Patchwork @ 2022-02-01 13:18 ` Patchwork 2022-02-01 13:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (3 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2022-02-01 13:18 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx == Series Details == Series: Compile out integrated URL : https://patchwork.freedesktop.org/series/99570/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Compile out integrated 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin ` (3 preceding siblings ...) 2022-02-01 13:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork @ 2022-02-01 13:47 ` Patchwork 2022-02-01 16:55 ` [Intel-gfx] [RFC 0/2] " Lucas De Marchi ` (2 subsequent siblings) 7 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2022-02-01 13:47 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 4477 bytes --] == Series Details == Series: Compile out integrated URL : https://patchwork.freedesktop.org/series/99570/ State : success == Summary == CI Bug Log - changes from CI_DRM_11172 -> Patchwork_22149 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/index.html Participating hosts (45 -> 44) ------------------------------ Additional (1): fi-pnv-d510 Missing (2): shard-tglu fi-bdw-samus Known issues ------------ Here are the changes found in Patchwork_22149 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_flink_basic@bad-flink: - fi-skl-6600u: [PASS][1] -> [FAIL][2] ([i915#4547]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-skl-6600u/igt@gem_flink_basic@bad-flink.html * igt@gem_huc_copy@huc-copy: - fi-pnv-d510: NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@verify-random: - fi-bsw-nick: NOTRUN -> [SKIP][4] ([fdo#109271]) +62 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-bsw-nick/igt@gem_lmem_swapping@verify-random.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [PASS][5] -> [INCOMPLETE][6] ([i915#3303]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html * igt@kms_chamelium@vga-edid-read: - fi-bsw-nick: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-bsw-nick/igt@kms_chamelium@vga-edid-read.html * igt@runner@aborted: - fi-hsw-4770: NOTRUN -> [FAIL][8] ([fdo#109271] / [i915#1436] / [i915#4312]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-hsw-4770/igt@runner@aborted.html #### Possible fixes #### * igt@gem_ctx_exec@basic: - fi-bsw-nick: [DMESG-WARN][9] ([i915#3428]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/fi-bsw-nick/igt@gem_ctx_exec@basic.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-bsw-nick/igt@gem_ctx_exec@basic.html #### Warnings #### * igt@i915_selftest@live@requests: - fi-blb-e6850: [DMESG-FAIL][11] ([i915#5026]) -> [DMESG-FAIL][12] ([i915#4528] / [i915#5026]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/fi-blb-e6850/igt@i915_selftest@live@requests.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/fi-blb-e6850/igt@i915_selftest@live@requests.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3428]: https://gitlab.freedesktop.org/drm/intel/issues/3428 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4547]: https://gitlab.freedesktop.org/drm/intel/issues/4547 [i915#4898]: https://gitlab.freedesktop.org/drm/intel/issues/4898 [i915#5026]: https://gitlab.freedesktop.org/drm/intel/issues/5026 Build changes ------------- * Linux: CI_DRM_11172 -> Patchwork_22149 CI-20190529: 20190529 CI_DRM_11172: 466c37c518256a1c79ed5f6ed4d3db1866c17910 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6337: 7c9c034619ef9dbfbfe041fbf3973a1cf1ac7a22 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22149: 528a41163c0e7f41362b7fcbb2b0934797df1e21 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 528a41163c0e jsl/ehl 15e05554122b igp kconfig == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/index.html [-- Attachment #2: Type: text/html, Size: 5404 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin ` (4 preceding siblings ...) 2022-02-01 13:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-02-01 16:55 ` Lucas De Marchi 2022-02-01 17:09 ` Jani Nikula 2022-02-01 17:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork 2022-02-02 11:51 ` [Intel-gfx] [RFC 0/2] " Tvrtko Ursulin 7 siblings, 1 reply; 19+ messages in thread From: Lucas De Marchi @ 2022-02-01 16:55 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, Michael Cheng On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > >Quicky and dirty hack based on some old ideas. Thought maybe the approach might >interest the Arm port guys. But with IS_GEN_RANGE removed easy gains are not so >big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I haven't looked >into that side. > > 3884664 449681 6720 4341065 423d49 i915.ko.tip > 3599989 429034 6688 4035711 3d947f i915.ko.noigp By these numbers probably it's hard to justify. Another thing to consider is that it's very common to have on the same system both integrated and discrete - doing this would remove at compile time any chance of driving the integrated one. Lucas De Marchi > >Note debug kconfig so everything is inflated. Whether or not the relative gain >would change with production kconfig I am not sure. > >P.S. >I was a bit curious there were no build errors around functions no longer used >so either there were none (would mean patch is not really that effective), or >something changed with compiler warnings/smarts. Haven't looked into it. > >Tvrtko Ursulin (2): > igp kconfig > jsl/ehl > > drivers/gpu/drm/i915/Kconfig | 5 + > drivers/gpu/drm/i915/Kconfig.platforms | 7 + > .../drm/i915/display/intel_ddi_buf_trans.c | 4 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- > drivers/gpu/drm/i915/i915_drv.h | 128 +++++++++++------- > drivers/gpu/drm/i915/i915_pci.c | 44 +++++- > 6 files changed, 134 insertions(+), 56 deletions(-) > create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms > >-- >2.32.0 > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-01 16:55 ` [Intel-gfx] [RFC 0/2] " Lucas De Marchi @ 2022-02-01 17:09 ` Jani Nikula 2022-02-01 17:28 ` Lucas De Marchi 0 siblings, 1 reply; 19+ messages in thread From: Jani Nikula @ 2022-02-01 17:09 UTC (permalink / raw) To: Lucas De Marchi, Tvrtko Ursulin; +Cc: Intel-gfx, Michael Cheng On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: > On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >>Quicky and dirty hack based on some old ideas. Thought maybe the approach might >>interest the Arm port guys. But with IS_GEN_RANGE removed easy gains are not so >>big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I haven't looked >>into that side. >> >> 3884664 449681 6720 4341065 423d49 i915.ko.tip >> 3599989 429034 6688 4035711 3d947f i915.ko.noigp > > By these numbers probably it's hard to justify. Another thing to consider > is that it's very common to have on the same system both > integrated and discrete - doing this would remove at compile time any > chance of driving the integrated one. I guess the point was, the arm systems won't have integrated, and it's anyway going to be a separate build. BR, Jani. > > Lucas De Marchi > >> >>Note debug kconfig so everything is inflated. Whether or not the relative gain >>would change with production kconfig I am not sure. >> >>P.S. >>I was a bit curious there were no build errors around functions no longer used >>so either there were none (would mean patch is not really that effective), or >>something changed with compiler warnings/smarts. Haven't looked into it. >> >>Tvrtko Ursulin (2): >> igp kconfig >> jsl/ehl >> >> drivers/gpu/drm/i915/Kconfig | 5 + >> drivers/gpu/drm/i915/Kconfig.platforms | 7 + >> .../drm/i915/display/intel_ddi_buf_trans.c | 4 +- >> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- >> drivers/gpu/drm/i915/i915_drv.h | 128 +++++++++++------- >> drivers/gpu/drm/i915/i915_pci.c | 44 +++++- >> 6 files changed, 134 insertions(+), 56 deletions(-) >> create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms >> >>-- >>2.32.0 >> -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-01 17:09 ` Jani Nikula @ 2022-02-01 17:28 ` Lucas De Marchi 2022-02-02 10:26 ` Tvrtko Ursulin 0 siblings, 1 reply; 19+ messages in thread From: Lucas De Marchi @ 2022-02-01 17:28 UTC (permalink / raw) To: Jani Nikula; +Cc: Intel-gfx, Michael Cheng On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >> On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>> >>>Quicky and dirty hack based on some old ideas. Thought maybe the approach might >>>interest the Arm port guys. But with IS_GEN_RANGE removed easy gains are not so >>>big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I haven't looked >>>into that side. >>> >>> 3884664 449681 6720 4341065 423d49 i915.ko.tip >>> 3599989 429034 6688 4035711 3d947f i915.ko.noigp >> >> By these numbers probably it's hard to justify. Another thing to consider >> is that it's very common to have on the same system both >> integrated and discrete - doing this would remove at compile time any >> chance of driving the integrated one. > >I guess the point was, the arm systems won't have integrated, and it's >anyway going to be a separate build. so probably the focus and argument here should not be about size reduction. From patch 1 I see: +config DRM_I915_INTEGRATED_GPU_SUPPORT + bool "Support integrated GPUs" + default y + depends on DRM_I915 + help + Include support for integrated GPUs. If it's something that depends on arch rather than providing an option in menuconfig, then I think it could be some interesting investigation. However, I can't see how it would help with removing some code paths in the driver (e.g. the clflush() calls we were talking about in another patch series) since the code elimination would all happen at link time. Lucas De Marchi > >BR, >Jani. > > >> >> Lucas De Marchi >> >>> >>>Note debug kconfig so everything is inflated. Whether or not the relative gain >>>would change with production kconfig I am not sure. >>> >>>P.S. >>>I was a bit curious there were no build errors around functions no longer used >>>so either there were none (would mean patch is not really that effective), or >>>something changed with compiler warnings/smarts. Haven't looked into it. >>> >>>Tvrtko Ursulin (2): >>> igp kconfig >>> jsl/ehl >>> >>> drivers/gpu/drm/i915/Kconfig | 5 + >>> drivers/gpu/drm/i915/Kconfig.platforms | 7 + >>> .../drm/i915/display/intel_ddi_buf_trans.c | 4 +- >>> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 2 +- >>> drivers/gpu/drm/i915/i915_drv.h | 128 +++++++++++------- >>> drivers/gpu/drm/i915/i915_pci.c | 44 +++++- >>> 6 files changed, 134 insertions(+), 56 deletions(-) >>> create mode 100644 drivers/gpu/drm/i915/Kconfig.platforms >>> >>>-- >>>2.32.0 >>> > >-- >Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-01 17:28 ` Lucas De Marchi @ 2022-02-02 10:26 ` Tvrtko Ursulin 2022-02-02 11:20 ` Jani Nikula 2022-02-02 16:26 ` Lucas De Marchi 0 siblings, 2 replies; 19+ messages in thread From: Tvrtko Ursulin @ 2022-02-02 10:26 UTC (permalink / raw) To: Lucas De Marchi, Jani Nikula; +Cc: Intel-gfx, Michael Cheng On 01/02/2022 17:28, Lucas De Marchi wrote: > On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >> On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>> On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>> >>>> Quicky and dirty hack based on some old ideas. Thought maybe the >>>> approach might >>>> interest the Arm port guys. But with IS_GEN_RANGE removed easy gains >>>> are not so >>>> big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I >>>> haven't looked >>>> into that side. >>>> >>>> 3884664 449681 6720 4341065 423d49 i915.ko.tip >>>> 3599989 429034 6688 4035711 3d947f i915.ko.noigp >>> >>> By these numbers probably it's hard to justify. Another thing to >>> consider >>> is that it's very common to have on the same system both >>> integrated and discrete - doing this would remove at compile time any >>> chance of driving the integrated one. >> >> I guess the point was, the arm systems won't have integrated, and it's >> anyway going to be a separate build. > > so probably the focus and argument here should not be about size > reduction. From patch 1 I see: > > +config DRM_I915_INTEGRATED_GPU_SUPPORT > + bool "Support integrated GPUs" > + default y > + depends on DRM_I915 > + help > + Include support for integrated GPUs. > > If it's something that depends on arch rather than providing an > option in menuconfig, then I think it could be some interesting > investigation. However, I can't see how it would help with removing > some code paths in the driver (e.g. the clflush() calls we were talking > about in another patch series) since the code elimination would all > happen at link time. Clflush class of problems is yet another orthogonal set of problems. Yes, idea was that the Kconfig option would be selected by Arm, or deselected by x86, whatever. But there is also a case for letting it be user visible. In general, I thought at least, we should look into not building/deploying binary code for irrelevant hardware on Arm builds. If that is clear and agreeable then I think the approach how to get there is really multi-pronged. 1) What you are partly doing with "clflush" type series. Make Arm relevant code paths actually compile on Arm. 2a) What I sent in this series - it's simple/easy dead code elimination from a single compilation unit. 2b) *If* we resurrected GRAPHICS_VER check where "ver" is part of the macro, eg. not doing "if (GRAPHICS_VER <=> N)" but "if (GRAPHICS_VERN)", or "if IS_GRAPHICS_VER(N, FOREVER)", then the same approach would be more effective. Because if N or range is the macro parameter, we can make it dead code based on Kconfig. This is what I demonstrated few years ago by being able to compile out ~3rd of a driver when selecting only execlists platforms, AFAIR. And which is why I was a bit unhappy this was getting removed not so long ago. 3) Complex step is putting LTO into use to allow dead code elimination between compilation units. Think: file1.c: RUNTIME_INFO->needs_blah = IS_PLATFORM && blah file2.c if (RUNTIME_INFO->needs_blah) ..dead code eliminated by LTO only.. Few years ago Andi Kleen had a proof of concept of KBuild LTO but I don't know what is the status of that. If LTO can be enabled then work from steps 2a&b automatically works much much better. 4) If LTO is not there yet maybe see how to slightly refactor the code so that we can completely drop compilation units from the Makefile. Drop files like gt/intel_ring_submission.c, or similar if we have or can create candidates. Regards, Tvrtko ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-02 10:26 ` Tvrtko Ursulin @ 2022-02-02 11:20 ` Jani Nikula 2022-02-02 12:17 ` Tvrtko Ursulin 2022-02-02 16:26 ` Lucas De Marchi 1 sibling, 1 reply; 19+ messages in thread From: Jani Nikula @ 2022-02-02 11:20 UTC (permalink / raw) To: Tvrtko Ursulin, Lucas De Marchi; +Cc: Intel-gfx, Michael Cheng On Wed, 02 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 01/02/2022 17:28, Lucas De Marchi wrote: >> On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >>> On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>> On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>> >>>>> Quicky and dirty hack based on some old ideas. Thought maybe the >>>>> approach might >>>>> interest the Arm port guys. But with IS_GEN_RANGE removed easy gains >>>>> are not so >>>>> big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I >>>>> haven't looked >>>>> into that side. >>>>> >>>>> 3884664 449681 6720 4341065 423d49 i915.ko.tip >>>>> 3599989 429034 6688 4035711 3d947f i915.ko.noigp >>>> >>>> By these numbers probably it's hard to justify. Another thing to >>>> consider >>>> is that it's very common to have on the same system both >>>> integrated and discrete - doing this would remove at compile time any >>>> chance of driving the integrated one. >>> >>> I guess the point was, the arm systems won't have integrated, and it's >>> anyway going to be a separate build. >> >> so probably the focus and argument here should not be about size >> reduction. From patch 1 I see: >> >> +config DRM_I915_INTEGRATED_GPU_SUPPORT >> + bool "Support integrated GPUs" >> + default y >> + depends on DRM_I915 >> + help >> + Include support for integrated GPUs. >> >> If it's something that depends on arch rather than providing an >> option in menuconfig, then I think it could be some interesting >> investigation. However, I can't see how it would help with removing >> some code paths in the driver (e.g. the clflush() calls we were talking >> about in another patch series) since the code elimination would all >> happen at link time. > > Clflush class of problems is yet another orthogonal set of problems. > > Yes, idea was that the Kconfig option would be selected by Arm, or > deselected by x86, whatever. But there is also a case for letting it be > user visible. > > In general, I thought at least, we should look into not > building/deploying binary code for irrelevant hardware on Arm builds. If > that is clear and agreeable then I think the approach how to get there > is really multi-pronged. > > 1) > What you are partly doing with "clflush" type series. Make Arm relevant > code paths actually compile on Arm. > > 2a) > What I sent in this series - it's simple/easy dead code elimination from > a single compilation unit. > > 2b) > *If* we resurrected GRAPHICS_VER check where "ver" is part of the macro, > eg. not doing "if (GRAPHICS_VER <=> N)" but "if (GRAPHICS_VERN)", or "if > IS_GRAPHICS_VER(N, FOREVER)", then the same approach would be more > effective. > > Because if N or range is the macro parameter, we can make it dead code > based on Kconfig. > > This is what I demonstrated few years ago by being able to compile out > ~3rd of a driver when selecting only execlists platforms, AFAIR. > > And which is why I was a bit unhappy this was getting removed not so > long ago. The main problem with that, as well as the Kconfig here, is maintenance. If it's fancy but unused, it's just added complexity for no benefit, just the drawbacks. Every change needs to take the complexity into account. If it's unused and untested, it's just going to bitrot anyway. For example, I think a config option for disabling igfx should have both build and runtime testing in place before we should consider taking on the burden of maintaining it. Otherwise it's just haphazard struggle, and the burden falls on a handful of interested people working on it on the side, occasionally fixing things as they break. And they'll break because nobody else cares. If someone shows up and says i915.ko is too big, they need to be serious enough to invest in maintaining the configurable size reductions, per target platform. BR, Jani. > > 3) > Complex step is putting LTO into use to allow dead code elimination > between compilation units. Think: > > file1.c: > RUNTIME_INFO->needs_blah = IS_PLATFORM && blah > > file2.c > if (RUNTIME_INFO->needs_blah) > ..dead code eliminated by LTO only.. > > Few years ago Andi Kleen had a proof of concept of KBuild LTO but I > don't know what is the status of that. If LTO can be enabled then work > from steps 2a&b automatically works much much better. > > 4) > If LTO is not there yet maybe see how to slightly refactor the code so > that we can completely drop compilation units from the Makefile. Drop > files like gt/intel_ring_submission.c, or similar if we have or can > create candidates. > > Regards, > > Tvrtko -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-02 11:20 ` Jani Nikula @ 2022-02-02 12:17 ` Tvrtko Ursulin 2022-02-02 12:41 ` Jani Nikula 0 siblings, 1 reply; 19+ messages in thread From: Tvrtko Ursulin @ 2022-02-02 12:17 UTC (permalink / raw) To: Jani Nikula, Lucas De Marchi; +Cc: Intel-gfx, Michael Cheng On 02/02/2022 11:20, Jani Nikula wrote: > On Wed, 02 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: >> On 01/02/2022 17:28, Lucas De Marchi wrote: >>> On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >>>> On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>>> On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>> >>>>>> Quicky and dirty hack based on some old ideas. Thought maybe the >>>>>> approach might >>>>>> interest the Arm port guys. But with IS_GEN_RANGE removed easy gains >>>>>> are not so >>>>>> big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I >>>>>> haven't looked >>>>>> into that side. >>>>>> >>>>>> 3884664 449681 6720 4341065 423d49 i915.ko.tip >>>>>> 3599989 429034 6688 4035711 3d947f i915.ko.noigp >>>>> >>>>> By these numbers probably it's hard to justify. Another thing to >>>>> consider >>>>> is that it's very common to have on the same system both >>>>> integrated and discrete - doing this would remove at compile time any >>>>> chance of driving the integrated one. >>>> >>>> I guess the point was, the arm systems won't have integrated, and it's >>>> anyway going to be a separate build. >>> >>> so probably the focus and argument here should not be about size >>> reduction. From patch 1 I see: >>> >>> +config DRM_I915_INTEGRATED_GPU_SUPPORT >>> + bool "Support integrated GPUs" >>> + default y >>> + depends on DRM_I915 >>> + help >>> + Include support for integrated GPUs. >>> >>> If it's something that depends on arch rather than providing an >>> option in menuconfig, then I think it could be some interesting >>> investigation. However, I can't see how it would help with removing >>> some code paths in the driver (e.g. the clflush() calls we were talking >>> about in another patch series) since the code elimination would all >>> happen at link time. >> >> Clflush class of problems is yet another orthogonal set of problems. >> >> Yes, idea was that the Kconfig option would be selected by Arm, or >> deselected by x86, whatever. But there is also a case for letting it be >> user visible. >> >> In general, I thought at least, we should look into not >> building/deploying binary code for irrelevant hardware on Arm builds. If >> that is clear and agreeable then I think the approach how to get there >> is really multi-pronged. >> >> 1) >> What you are partly doing with "clflush" type series. Make Arm relevant >> code paths actually compile on Arm. >> >> 2a) >> What I sent in this series - it's simple/easy dead code elimination from >> a single compilation unit. >> >> 2b) >> *If* we resurrected GRAPHICS_VER check where "ver" is part of the macro, >> eg. not doing "if (GRAPHICS_VER <=> N)" but "if (GRAPHICS_VERN)", or "if >> IS_GRAPHICS_VER(N, FOREVER)", then the same approach would be more >> effective. >> >> Because if N or range is the macro parameter, we can make it dead code >> based on Kconfig. >> >> This is what I demonstrated few years ago by being able to compile out >> ~3rd of a driver when selecting only execlists platforms, AFAIR. >> >> And which is why I was a bit unhappy this was getting removed not so >> long ago. > > The main problem with that, as well as the Kconfig here, is maintenance. > > If it's fancy but unused, it's just added complexity for no benefit, > just the drawbacks. Every change needs to take the complexity into > account. If it's unused and untested, it's just going to bitrot anyway. > > For example, I think a config option for disabling igfx should have both > build and runtime testing in place before we should consider taking on > the burden of maintaining it. Otherwise it's just haphazard struggle, > and the burden falls on a handful of interested people working on it on > the side, occasionally fixing things as they break. And they'll break > because nobody else cares. > > If someone shows up and says i915.ko is too big, they need to be serious > enough to invest in maintaining the configurable size reductions, per > target platform. Yeah no disagreement for the most part. Whether there is a cheap way (as in maintenance/intrusiveness) which brings gains large enough. In my view it is also not a question of "too big" per se, but a question of professional pride of doing things properly, even if it is hard, instead of padding the binaries with dead code and sending them on rounds over the world, to "use electrons" unreachable on uncountable hypothetical customer machines and travel as updates over undersea cables for no use. :D Just because we, sitting on the source/upstream, decided it's too hard. Not pressuring anything though, we are not quite there yet to worry about scale deployments of Intel discrete on !x86. There is time. :) I've thrown some seeds out there, if they don't take, they don't. It is fine to tackle the "make it build and work" steps first. Regards, Tvrtko ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-02 12:17 ` Tvrtko Ursulin @ 2022-02-02 12:41 ` Jani Nikula 0 siblings, 0 replies; 19+ messages in thread From: Jani Nikula @ 2022-02-02 12:41 UTC (permalink / raw) To: Tvrtko Ursulin, Lucas De Marchi; +Cc: Intel-gfx, Michael Cheng On Wed, 02 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: > On 02/02/2022 11:20, Jani Nikula wrote: >> On Wed, 02 Feb 2022, Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> wrote: >>> On 01/02/2022 17:28, Lucas De Marchi wrote: >>>> On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >>>>> On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>>>> On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>>> >>>>>>> Quicky and dirty hack based on some old ideas. Thought maybe the >>>>>>> approach might >>>>>>> interest the Arm port guys. But with IS_GEN_RANGE removed easy gains >>>>>>> are not so >>>>>>> big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I >>>>>>> haven't looked >>>>>>> into that side. >>>>>>> >>>>>>> 3884664 449681 6720 4341065 423d49 i915.ko.tip >>>>>>> 3599989 429034 6688 4035711 3d947f i915.ko.noigp >>>>>> >>>>>> By these numbers probably it's hard to justify. Another thing to >>>>>> consider >>>>>> is that it's very common to have on the same system both >>>>>> integrated and discrete - doing this would remove at compile time any >>>>>> chance of driving the integrated one. >>>>> >>>>> I guess the point was, the arm systems won't have integrated, and it's >>>>> anyway going to be a separate build. >>>> >>>> so probably the focus and argument here should not be about size >>>> reduction. From patch 1 I see: >>>> >>>> +config DRM_I915_INTEGRATED_GPU_SUPPORT >>>> + bool "Support integrated GPUs" >>>> + default y >>>> + depends on DRM_I915 >>>> + help >>>> + Include support for integrated GPUs. >>>> >>>> If it's something that depends on arch rather than providing an >>>> option in menuconfig, then I think it could be some interesting >>>> investigation. However, I can't see how it would help with removing >>>> some code paths in the driver (e.g. the clflush() calls we were talking >>>> about in another patch series) since the code elimination would all >>>> happen at link time. >>> >>> Clflush class of problems is yet another orthogonal set of problems. >>> >>> Yes, idea was that the Kconfig option would be selected by Arm, or >>> deselected by x86, whatever. But there is also a case for letting it be >>> user visible. >>> >>> In general, I thought at least, we should look into not >>> building/deploying binary code for irrelevant hardware on Arm builds. If >>> that is clear and agreeable then I think the approach how to get there >>> is really multi-pronged. >>> >>> 1) >>> What you are partly doing with "clflush" type series. Make Arm relevant >>> code paths actually compile on Arm. >>> >>> 2a) >>> What I sent in this series - it's simple/easy dead code elimination from >>> a single compilation unit. >>> >>> 2b) >>> *If* we resurrected GRAPHICS_VER check where "ver" is part of the macro, >>> eg. not doing "if (GRAPHICS_VER <=> N)" but "if (GRAPHICS_VERN)", or "if >>> IS_GRAPHICS_VER(N, FOREVER)", then the same approach would be more >>> effective. >>> >>> Because if N or range is the macro parameter, we can make it dead code >>> based on Kconfig. >>> >>> This is what I demonstrated few years ago by being able to compile out >>> ~3rd of a driver when selecting only execlists platforms, AFAIR. >>> >>> And which is why I was a bit unhappy this was getting removed not so >>> long ago. >> >> The main problem with that, as well as the Kconfig here, is maintenance. >> >> If it's fancy but unused, it's just added complexity for no benefit, >> just the drawbacks. Every change needs to take the complexity into >> account. If it's unused and untested, it's just going to bitrot anyway. >> >> For example, I think a config option for disabling igfx should have both >> build and runtime testing in place before we should consider taking on >> the burden of maintaining it. Otherwise it's just haphazard struggle, >> and the burden falls on a handful of interested people working on it on >> the side, occasionally fixing things as they break. And they'll break >> because nobody else cares. >> >> If someone shows up and says i915.ko is too big, they need to be serious >> enough to invest in maintaining the configurable size reductions, per >> target platform. > > Yeah no disagreement for the most part. > > Whether there is a cheap way (as in maintenance/intrusiveness) which > brings gains large enough. > > In my view it is also not a question of "too big" per se, but a question > of professional pride of doing things properly, even if it is hard, > instead of padding the binaries with dead code and sending them on > rounds over the world, to "use electrons" unreachable on uncountable > hypothetical customer machines and travel as updates over undersea > cables for no use. :D Just because we, sitting on the source/upstream, > decided it's too hard. Well, not because it's too hard, but mostly because of picking the battles? Also a matter of taste in what constitutes as professional pride. If it's worth doing, it's worth doing properly? But I guess we are, mostly, on the same page here. BR, Jani. > > Not pressuring anything though, we are not quite there yet to worry > about scale deployments of Intel discrete on !x86. There is time. :) > I've thrown some seeds out there, if they don't take, they don't. It is > fine to tackle the "make it build and work" steps first. > > Regards, > > Tvrtko -- Jani Nikula, Intel Open Source Graphics Center ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-02 10:26 ` Tvrtko Ursulin 2022-02-02 11:20 ` Jani Nikula @ 2022-02-02 16:26 ` Lucas De Marchi 2022-02-08 10:31 ` Tvrtko Ursulin 1 sibling, 1 reply; 19+ messages in thread From: Lucas De Marchi @ 2022-02-02 16:26 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, Michael Cheng On Wed, Feb 02, 2022 at 10:26:46AM +0000, Tvrtko Ursulin wrote: > >On 01/02/2022 17:28, Lucas De Marchi wrote: >>On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >>>On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>>On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>> >>>>>Quicky and dirty hack based on some old ideas. Thought maybe >>>>>the approach might >>>>>interest the Arm port guys. But with IS_GEN_RANGE removed easy >>>>>gains are not so >>>>>big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but >>>>>I haven't looked >>>>>into that side. >>>>> >>>>>3884664 449681 6720 4341065 423d49 i915.ko.tip >>>>>3599989 429034 6688 4035711 3d947f i915.ko.noigp >>>> >>>>By these numbers probably it's hard to justify. Another thing to >>>>consider >>>>is that it's very common to have on the same system both >>>>integrated and discrete - doing this would remove at compile time any >>>>chance of driving the integrated one. >>> >>>I guess the point was, the arm systems won't have integrated, and it's >>>anyway going to be a separate build. >> >>so probably the focus and argument here should not be about size >>reduction. From patch 1 I see: >> >>+config DRM_I915_INTEGRATED_GPU_SUPPORT >>+ bool "Support integrated GPUs" >>+ default y >>+ depends on DRM_I915 >>+ help >>+ Include support for integrated GPUs. >> >>If it's something that depends on arch rather than providing an >>option in menuconfig, then I think it could be some interesting >>investigation. However, I can't see how it would help with removing >>some code paths in the driver (e.g. the clflush() calls we were talking >>about in another patch series) since the code elimination would all >>happen at link time. > >Clflush class of problems is yet another orthogonal set of problems. > >Yes, idea was that the Kconfig option would be selected by Arm, or >deselected by x86, whatever. But there is also a case for letting it >be user visible. > >In general, I thought at least, we should look into not >building/deploying binary code for irrelevant hardware on Arm builds. >If that is clear and agreeable then I think the approach how to get >there is really multi-pronged. > >1) >What you are partly doing with "clflush" type series. Make Arm >relevant code paths actually compile on Arm. to be clear, the goal is to be more architecture independent and this is being tested with arm64. > >2a) >What I sent in this series - it's simple/easy dead code elimination >from a single compilation unit. > >2b) >*If* we resurrected GRAPHICS_VER check where "ver" is part of the >macro, eg. not doing "if (GRAPHICS_VER <=> N)" but "if >(GRAPHICS_VERN)", or "if IS_GRAPHICS_VER(N, FOREVER)", then the same >approach would be more effective. > >Because if N or range is the macro parameter, we can make it dead code >based on Kconfig. yes I remember that. But when it was done the IS_GRAPHICS_VER() was already not much used. I doubt the handful places it was used in would change much of the overall picture we had at that point. >This is what I demonstrated few years ago by being able to compile out >~3rd of a driver when selecting only execlists platforms, AFAIR. > >And which is why I was a bit unhappy this was getting removed not so >long ago. > >3) >Complex step is putting LTO into use to allow dead code elimination >between compilation units. Think: > >file1.c: >RUNTIME_INFO->needs_blah = IS_PLATFORM && blah > >file2.c >if (RUNTIME_INFO->needs_blah) > ..dead code eliminated by LTO only.. > >Few years ago Andi Kleen had a proof of concept of KBuild LTO but I >don't know what is the status of that. If LTO can be enabled then work >from steps 2a&b automatically works much much better. > >4) >If LTO is not there yet maybe see how to slightly refactor the code so >that we can completely drop compilation units from the Makefile. Drop >files like gt/intel_ring_submission.c, or similar if we have or can >create candidates. I think this is something we have to do and to go after. I think it's more future-proof to organize the code to have a better separation of platforms, instead of relying on the linker to do the dead code elimination based on user selection. I'm fine with compiling out stuff on i915 right now because "this can only and will ever (as far as we know) work on x86". I'm more reluctant about adding a build option though. For the same reasons Jani mentioned and that it suddenly may open the doors for a matrix of configuration (e.g. build with/without display, or rc6, or dsi, or name-the-feature-you-dont-want). Lucas De Marchi > >Regards, > >Tvrtko ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-02 16:26 ` Lucas De Marchi @ 2022-02-08 10:31 ` Tvrtko Ursulin 2022-02-08 20:34 ` Lucas De Marchi 0 siblings, 1 reply; 19+ messages in thread From: Tvrtko Ursulin @ 2022-02-08 10:31 UTC (permalink / raw) To: Lucas De Marchi; +Cc: Jani Nikula, Intel-gfx, Michael Cheng On 02/02/2022 16:26, Lucas De Marchi wrote: > On Wed, Feb 02, 2022 at 10:26:46AM +0000, Tvrtko Ursulin wrote: >> >> On 01/02/2022 17:28, Lucas De Marchi wrote: >>> On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >>>> On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>>> On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>> >>>>>> Quicky and dirty hack based on some old ideas. Thought maybe the >>>>>> approach might >>>>>> interest the Arm port guys. But with IS_GEN_RANGE removed easy >>>>>> gains are not so >>>>>> big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I >>>>>> haven't looked >>>>>> into that side. >>>>>> >>>>>> 3884664 449681 6720 4341065 423d49 i915.ko.tip >>>>>> 3599989 429034 6688 4035711 3d947f i915.ko.noigp >>>>> >>>>> By these numbers probably it's hard to justify. Another thing to >>>>> consider >>>>> is that it's very common to have on the same system both >>>>> integrated and discrete - doing this would remove at compile time any >>>>> chance of driving the integrated one. >>>> >>>> I guess the point was, the arm systems won't have integrated, and it's >>>> anyway going to be a separate build. >>> >>> so probably the focus and argument here should not be about size >>> reduction. From patch 1 I see: >>> >>> +config DRM_I915_INTEGRATED_GPU_SUPPORT >>> + bool "Support integrated GPUs" >>> + default y >>> + depends on DRM_I915 >>> + help >>> + Include support for integrated GPUs. >>> >>> If it's something that depends on arch rather than providing an >>> option in menuconfig, then I think it could be some interesting >>> investigation. However, I can't see how it would help with removing >>> some code paths in the driver (e.g. the clflush() calls we were talking >>> about in another patch series) since the code elimination would all >>> happen at link time. >> >> Clflush class of problems is yet another orthogonal set of problems. >> >> Yes, idea was that the Kconfig option would be selected by Arm, or >> deselected by x86, whatever. But there is also a case for letting it >> be user visible. >> >> In general, I thought at least, we should look into not >> building/deploying binary code for irrelevant hardware on Arm builds. >> If that is clear and agreeable then I think the approach how to get >> there is really multi-pronged. >> >> 1) >> What you are partly doing with "clflush" type series. Make Arm >> relevant code paths actually compile on Arm. > > to be clear, the goal is to be more architecture independent > and this is being tested with arm64. > >> >> 2a) >> What I sent in this series - it's simple/easy dead code elimination >> from a single compilation unit. >> >> 2b) >> *If* we resurrected GRAPHICS_VER check where "ver" is part of the >> macro, eg. not doing "if (GRAPHICS_VER <=> N)" but "if >> (GRAPHICS_VERN)", or "if IS_GRAPHICS_VER(N, FOREVER)", then the same >> approach would be more effective. >> >> Because if N or range is the macro parameter, we can make it dead code >> based on Kconfig. > > yes I remember that. But when it was done the IS_GRAPHICS_VER() was > already not much used. I doubt the handful places it was used in would > change much of the overall picture we had at that point. Right, I was referring to the time when N is inside the macro. Like before IS_GEN(p, N) was replaced with GRAPHICS_VER, when N went outside the macro. >> This is what I demonstrated few years ago by being able to compile out >> ~3rd of a driver when selecting only execlists platforms, AFAIR. >> >> And which is why I was a bit unhappy this was getting removed not so >> long ago. >> >> 3) >> Complex step is putting LTO into use to allow dead code elimination >> between compilation units. Think: >> >> file1.c: >> RUNTIME_INFO->needs_blah = IS_PLATFORM && blah >> >> file2.c >> if (RUNTIME_INFO->needs_blah) >> ..dead code eliminated by LTO only.. >> >> Few years ago Andi Kleen had a proof of concept of KBuild LTO but I >> don't know what is the status of that. If LTO can be enabled then work >> from steps 2a&b automatically works much much better. >> >> 4) >> If LTO is not there yet maybe see how to slightly refactor the code so >> that we can completely drop compilation units from the Makefile. Drop >> files like gt/intel_ring_submission.c, or similar if we have or can >> create candidates. > > I think this is something we have to do and to go after. I think it's > more future-proof to organize the code to have a better separation of > platforms, instead of relying on the linker to do the dead code > elimination based on user selection. Yes, definitely high level refactor. I just think it can't be fully done and some dead code elimination is cheap enough to have to handle the remaining parts. > I'm fine with compiling out stuff on i915 right now because "this can > only and will ever (as far as we know) work on x86". I'm more reluctant > about adding a build option though. For the same reasons Jani mentioned > and that it suddenly may open the doors for a matrix of configuration > (e.g. build with/without display, or rc6, or dsi, or > name-the-feature-you-dont-want). Yeah okay, I was not saying it absolutely needs to be user visible. Just that it could be argued it could be. Think people building custom kernels and selecting AMD CPU and having Intel discrete graphics. Regards, Tvrtko ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-08 10:31 ` Tvrtko Ursulin @ 2022-02-08 20:34 ` Lucas De Marchi 0 siblings, 0 replies; 19+ messages in thread From: Lucas De Marchi @ 2022-02-08 20:34 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, Michael Cheng On Tue, Feb 08, 2022 at 10:31:10AM +0000, Tvrtko Ursulin wrote: > >On 02/02/2022 16:26, Lucas De Marchi wrote: >>On Wed, Feb 02, 2022 at 10:26:46AM +0000, Tvrtko Ursulin wrote: >>> >>>On 01/02/2022 17:28, Lucas De Marchi wrote: >>>>On Tue, Feb 01, 2022 at 07:09:14PM +0200, Jani Nikula wrote: >>>>>On Tue, 01 Feb 2022, Lucas De Marchi <lucas.demarchi@intel.com> wrote: >>>>>>On Tue, Feb 01, 2022 at 11:15:31AM +0000, Tvrtko Ursulin wrote: >>>>>>>From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >>>>>>> >>>>>>>Quicky and dirty hack based on some old ideas. Thought >>>>>>>maybe the approach might >>>>>>>interest the Arm port guys. But with IS_GEN_RANGE removed >>>>>>>easy gains are not so >>>>>>>big so meh.. Maybe some more easy wins with IS_DISPLAY_VER >>>>>>>but I haven't looked >>>>>>>into that side. >>>>>>> >>>>>>>3884664 449681 6720 4341065 423d49 i915.ko.tip >>>>>>>3599989 429034 6688 4035711 3d947f i915.ko.noigp >>>>>> >>>>>>By these numbers probably it's hard to justify. Another >>>>>>thing to consider >>>>>>is that it's very common to have on the same system both >>>>>>integrated and discrete - doing this would remove at compile time any >>>>>>chance of driving the integrated one. >>>>> >>>>>I guess the point was, the arm systems won't have integrated, and it's >>>>>anyway going to be a separate build. >>>> >>>>so probably the focus and argument here should not be about size >>>>reduction. From patch 1 I see: >>>> >>>>+config DRM_I915_INTEGRATED_GPU_SUPPORT >>>>+ bool "Support integrated GPUs" >>>>+ default y >>>>+ depends on DRM_I915 >>>>+ help >>>>+ Include support for integrated GPUs. >>>> >>>>If it's something that depends on arch rather than providing an >>>>option in menuconfig, then I think it could be some interesting >>>>investigation. However, I can't see how it would help with removing >>>>some code paths in the driver (e.g. the clflush() calls we were talking >>>>about in another patch series) since the code elimination would all >>>>happen at link time. >>> >>>Clflush class of problems is yet another orthogonal set of problems. >>> >>>Yes, idea was that the Kconfig option would be selected by Arm, or >>>deselected by x86, whatever. But there is also a case for letting >>>it be user visible. >>> >>>In general, I thought at least, we should look into not >>>building/deploying binary code for irrelevant hardware on Arm >>>builds. If that is clear and agreeable then I think the approach >>>how to get there is really multi-pronged. >>> >>>1) >>>What you are partly doing with "clflush" type series. Make Arm >>>relevant code paths actually compile on Arm. >> >>to be clear, the goal is to be more architecture independent >>and this is being tested with arm64. >> >>> >>>2a) >>>What I sent in this series - it's simple/easy dead code >>>elimination from a single compilation unit. >>> >>>2b) >>>*If* we resurrected GRAPHICS_VER check where "ver" is part of the >>>macro, eg. not doing "if (GRAPHICS_VER <=> N)" but "if >>>(GRAPHICS_VERN)", or "if IS_GRAPHICS_VER(N, FOREVER)", then the >>>same approach would be more effective. >>> >>>Because if N or range is the macro parameter, we can make it dead >>>code based on Kconfig. >> >>yes I remember that. But when it was done the IS_GRAPHICS_VER() was >>already not much used. I doubt the handful places it was used in would >>change much of the overall picture we had at that point. > >Right, I was referring to the time when N is inside the macro. Like >before IS_GEN(p, N) was replaced with GRAPHICS_VER, when N went >outside the macro. > >>>This is what I demonstrated few years ago by being able to compile >>>out ~3rd of a driver when selecting only execlists platforms, >>>AFAIR. >>> >>>And which is why I was a bit unhappy this was getting removed not >>>so long ago. >>> >>>3) >>>Complex step is putting LTO into use to allow dead code >>>elimination between compilation units. Think: >>> >>>file1.c: >>>RUNTIME_INFO->needs_blah = IS_PLATFORM && blah >>> >>>file2.c >>>if (RUNTIME_INFO->needs_blah) >>> ..dead code eliminated by LTO only.. >>> >>>Few years ago Andi Kleen had a proof of concept of KBuild LTO but >>>I don't know what is the status of that. If LTO can be enabled >>>then work from steps 2a&b automatically works much much better. >>> >>>4) >>>If LTO is not there yet maybe see how to slightly refactor the >>>code so that we can completely drop compilation units from the >>>Makefile. Drop files like gt/intel_ring_submission.c, or similar >>>if we have or can create candidates. >> >>I think this is something we have to do and to go after. I think it's >>more future-proof to organize the code to have a better separation of >>platforms, instead of relying on the linker to do the dead code >>elimination based on user selection. > >Yes, definitely high level refactor. I just think it can't be fully >done and some dead code elimination is cheap enough to have to handle >the remaining parts. > >>I'm fine with compiling out stuff on i915 right now because "this can >>only and will ever (as far as we know) work on x86". I'm more reluctant >>about adding a build option though. For the same reasons Jani mentioned >>and that it suddenly may open the doors for a matrix of configuration >>(e.g. build with/without display, or rc6, or dsi, or >>name-the-feature-you-dont-want). > >Yeah okay, I was not saying it absolutely needs to be user visible. >Just that it could be argued it could be. Think people building custom >kernels and selecting AMD CPU and having Intel discrete graphics. maybe start with the non-user-visible: make the config selection depend on arch. Depending how it goes, we then allow it to be configurable in future. Lucas De Marchi > >Regards, > >Tvrtko ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Compile out integrated 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin ` (5 preceding siblings ...) 2022-02-01 16:55 ` [Intel-gfx] [RFC 0/2] " Lucas De Marchi @ 2022-02-01 17:37 ` Patchwork 2022-02-02 11:51 ` [Intel-gfx] [RFC 0/2] " Tvrtko Ursulin 7 siblings, 0 replies; 19+ messages in thread From: Patchwork @ 2022-02-01 17:37 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30245 bytes --] == Series Details == Series: Compile out integrated URL : https://patchwork.freedesktop.org/series/99570/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11172_full -> Patchwork_22149_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_22149_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22149_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (12 -> 11) ------------------------------ Missing (1): shard-rkl Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22149_full: ### IGT changes ### #### Possible regressions #### * igt@i915_suspend@fence-restore-untiled: - shard-skl: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl4/igt@i915_suspend@fence-restore-untiled.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/igt@i915_suspend@fence-restore-untiled.html * igt@kms_setmode@basic: - shard-skl: NOTRUN -> [WARN][3] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@kms_setmode@basic.html Known issues ------------ Here are the changes found in Patchwork_22149_full that come from known issues: ### CI changes ### #### Possible fixes #### * boot: - shard-skl: ([PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [FAIL][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26], [PASS][27]) -> ([PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl9/boot.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl9/boot.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl9/boot.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl9/boot.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl8/boot.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl8/boot.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl7/boot.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl7/boot.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl7/boot.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl6/boot.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl6/boot.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl6/boot.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl4/boot.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl4/boot.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl4/boot.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl3/boot.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl3/boot.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl3/boot.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl1/boot.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl1/boot.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl10/boot.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl10/boot.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl10/boot.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl10/boot.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl7/boot.html [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl7/boot.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl7/boot.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl6/boot.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl6/boot.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl6/boot.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/boot.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/boot.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/boot.html [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/boot.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/boot.html [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/boot.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl1/boot.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl1/boot.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl1/boot.html [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl10/boot.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl10/boot.html [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/boot.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl9/boot.html [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl9/boot.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl9/boot.html [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/boot.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/boot.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/boot.html ### IGT changes ### #### Issues hit #### * igt@gem_exec_balancer@parallel: - shard-iclb: [PASS][52] -> [SKIP][53] ([i915#4525]) +1 similar issue [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-iclb1/igt@gem_exec_balancer@parallel.html [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb8/igt@gem_exec_balancer@parallel.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [PASS][54] -> [FAIL][55] ([i915#2842]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl7/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: [PASS][56] -> [FAIL][57] ([i915#2842]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs1.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_schedule@preempt-other-chain@vecs0: - shard-skl: [PASS][58] -> [DMESG-WARN][59] ([i915#1982]) [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl4/igt@gem_exec_schedule@preempt-other-chain@vecs0.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/igt@gem_exec_schedule@preempt-other-chain@vecs0.html * igt@gem_lmem_swapping@basic: - shard-kbl: NOTRUN -> [SKIP][60] ([fdo#109271] / [i915#4613]) +2 similar issues [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl4/igt@gem_lmem_swapping@basic.html * igt@gem_lmem_swapping@parallel-random: - shard-skl: NOTRUN -> [SKIP][61] ([fdo#109271] / [i915#4613]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@gem_lmem_swapping@parallel-random.html * igt@gem_lmem_swapping@parallel-random-engines: - shard-tglb: NOTRUN -> [SKIP][62] ([i915#4613]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@gem_lmem_swapping@parallel-random-engines.html * igt@gem_lmem_swapping@verify: - shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#4613]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl6/igt@gem_lmem_swapping@verify.html * igt@gem_userptr_blits@dmabuf-sync: - shard-kbl: NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#3323]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@gem_userptr_blits@dmabuf-sync.html - shard-tglb: NOTRUN -> [SKIP][65] ([i915#3323]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@gem_userptr_blits@dmabuf-sync.html * igt@gem_userptr_blits@readonly-pwrite-unsync: - shard-iclb: NOTRUN -> [SKIP][66] ([i915#3297]) +1 similar issue [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@gem_userptr_blits@readonly-pwrite-unsync.html * igt@gen9_exec_parse@bb-large: - shard-tglb: NOTRUN -> [SKIP][67] ([i915#2527] / [i915#2856]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@gen9_exec_parse@bb-large.html * igt@gen9_exec_parse@unaligned-jump: - shard-iclb: NOTRUN -> [SKIP][68] ([i915#2856]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@gen9_exec_parse@unaligned-jump.html * igt@i915_pm_dc@dc3co-vpb-simulation: - shard-tglb: NOTRUN -> [SKIP][69] ([i915#1904]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@i915_pm_dc@dc3co-vpb-simulation.html * igt@kms_big_fb@linear-32bpp-rotate-0: - shard-glk: [PASS][70] -> [DMESG-WARN][71] ([i915#118]) [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-glk2/igt@kms_big_fb@linear-32bpp-rotate-0.html [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-glk9/igt@kms_big_fb@linear-32bpp-rotate-0.html * igt@kms_big_fb@x-tiled-16bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][72] ([fdo#110725] / [fdo#111614]) [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][73] ([i915#3743]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip: - shard-kbl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3777]) +3 similar issues [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@kms_big_fb@x-tiled-max-hw-stride-32bpp-rotate-180-hflip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][75] ([i915#3763]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip: - shard-iclb: NOTRUN -> [SKIP][76] ([fdo#110723]) +1 similar issue [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb8/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-0-hflip.html * igt@kms_big_joiner@basic: - shard-iclb: NOTRUN -> [SKIP][77] ([i915#2705]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_big_joiner@basic.html * igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc: - shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [i915#3886]) +7 similar issues [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl4/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#3886]) +3 similar issues [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/igt@kms_ccs@pipe-a-random-ccs-data-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs: - shard-tglb: NOTRUN -> [SKIP][80] ([fdo#111615] / [i915#3689]) +2 similar issues [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-iclb: NOTRUN -> [SKIP][81] ([fdo#109278] / [i915#3886]) +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html - shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271] / [i915#3886]) +3 similar issues [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs: - shard-tglb: NOTRUN -> [SKIP][83] ([i915#3689]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs: - shard-iclb: NOTRUN -> [SKIP][84] ([fdo#109278]) +11 similar issues [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_ccs@pipe-d-crc-primary-basic-yf_tiled_ccs.html * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red: - shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271] / [fdo#111827]) +17 similar issues [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl6/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-blue-to-red: - shard-apl: NOTRUN -> [SKIP][86] ([fdo#109271] / [fdo#111827]) +1 similar issue [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl7/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html - shard-iclb: NOTRUN -> [SKIP][87] ([fdo#109284] / [fdo#111827]) +1 similar issue [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_color_chamelium@pipe-b-ctm-blue-to-red.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-skl: NOTRUN -> [SKIP][88] ([fdo#109271] / [fdo#111827]) +10 similar issues [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-b-degamma: - shard-tglb: NOTRUN -> [SKIP][89] ([fdo#109284] / [fdo#111827]) +2 similar issues [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_color_chamelium@pipe-b-degamma.html * igt@kms_content_protection@legacy: - shard-kbl: NOTRUN -> [TIMEOUT][90] ([i915#1319]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl4/igt@kms_content_protection@legacy.html * igt@kms_content_protection@mei_interface: - shard-iclb: NOTRUN -> [SKIP][91] ([fdo#109300] / [fdo#111066]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_content_protection@mei_interface.html * igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen: - shard-tglb: NOTRUN -> [SKIP][92] ([i915#3359]) [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-32x10-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-suspend: - shard-kbl: NOTRUN -> [DMESG-WARN][93] ([i915#180]) +1 similar issue [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html * igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding: - shard-tglb: NOTRUN -> [SKIP][94] ([fdo#109279] / [i915#3359]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding.html * igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding: - shard-iclb: NOTRUN -> [SKIP][95] ([fdo#109278] / [fdo#109279]) +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb8/igt@kms_cursor_crc@pipe-c-cursor-512x512-sliding.html * igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen: - shard-apl: NOTRUN -> [SKIP][96] ([fdo#109271]) +70 similar issues [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl6/igt@kms_cursor_crc@pipe-d-cursor-max-size-onscreen.html * igt@kms_cursor_crc@pipe-d-cursor-suspend: - shard-kbl: NOTRUN -> [SKIP][97] ([fdo#109271]) +176 similar issues [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html * igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge: - shard-skl: NOTRUN -> [SKIP][98] ([fdo#109271]) +124 similar issues [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@kms_cursor_edge_walk@pipe-d-128x128-right-edge.html * igt@kms_cursor_legacy@cursorb-vs-flipb-legacy: - shard-iclb: NOTRUN -> [SKIP][99] ([fdo#109274] / [fdo#109278]) [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_cursor_legacy@cursorb-vs-flipb-legacy.html * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size: - shard-skl: NOTRUN -> [FAIL][100] ([i915#2346] / [i915#533]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: [PASS][101] -> [INCOMPLETE][102] ([i915#180] / [i915#636]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-kbl3/igt@kms_fbcon_fbt@fbc-suspend.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-blocking-absolute-wf_vblank: - shard-tglb: NOTRUN -> [SKIP][103] ([fdo#109274] / [fdo#111825]) +1 similar issue [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_flip@2x-blocking-absolute-wf_vblank.html * igt@kms_flip@2x-blocking-wf_vblank: - shard-iclb: NOTRUN -> [SKIP][104] ([fdo#109274]) +3 similar issues [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_flip@2x-blocking-wf_vblank.html * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1: - shard-skl: [PASS][105] -> [FAIL][106] ([i915#2122]) [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl3/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl8/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1: - shard-apl: [PASS][107] -> [DMESG-WARN][108] ([i915#180]) +3 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html - shard-kbl: [PASS][109] -> [INCOMPLETE][110] ([i915#636]) [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-kbl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html * igt@kms_flip@flip-vs-suspend@c-dp1: - shard-kbl: [PASS][111] -> [DMESG-WARN][112] ([i915#180]) +4 similar issues [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-kbl4/igt@kms_flip@flip-vs-suspend@c-dp1.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl6/igt@kms_flip@flip-vs-suspend@c-dp1.html * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling: - shard-glk: [PASS][113] -> [FAIL][114] ([i915#4911]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-glk7/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt: - shard-iclb: NOTRUN -> [SKIP][115] ([fdo#109280]) +11 similar issues [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-blt.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc: - shard-tglb: NOTRUN -> [SKIP][116] ([fdo#109280] / [fdo#111825]) +5 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-wc.html * igt@kms_hdr@bpc-switch-dpms: - shard-skl: NOTRUN -> [FAIL][117] ([i915#1188]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl9/igt@kms_hdr@bpc-switch-dpms.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d: - shard-kbl: NOTRUN -> [SKIP][118] ([fdo#109271] / [i915#533]) +2 similar issues [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-d.html * igt@kms_plane_alpha_blend@pipe-a-alpha-basic: - shard-apl: NOTRUN -> [FAIL][119] ([fdo#108145] / [i915#265]) +1 similar issue [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl6/igt@kms_plane_alpha_blend@pipe-a-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb: - shard-skl: NOTRUN -> [FAIL][120] ([fdo#108145] / [i915#265]) +1 similar issue [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-kbl: NOTRUN -> [FAIL][121] ([fdo#108145] / [i915#265]) [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_plane_lowres@pipe-b-tiling-y: - shard-iclb: NOTRUN -> [SKIP][122] ([i915#3536]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_plane_lowres@pipe-b-tiling-y.html * igt@kms_plane_multiple@atomic-pipe-c-tiling-yf: - shard-tglb: NOTRUN -> [SKIP][123] ([fdo#111615]) [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_plane_multiple@atomic-pipe-c-tiling-yf.html * igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area: - shard-skl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#658]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html * igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area: - shard-apl: NOTRUN -> [SKIP][125] ([fdo#109271] / [i915#658]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl2/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-kbl: NOTRUN -> [SKIP][126] ([fdo#109271] / [i915#658]) +1 similar issue [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl4/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@psr2_basic: - shard-iclb: [PASS][127] -> [SKIP][128] ([fdo#109441]) +1 similar issue [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-iclb2/igt@kms_psr@psr2_basic.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb6/igt@kms_psr@psr2_basic.html * igt@kms_psr@psr2_primary_mmap_gtt: - shard-tglb: NOTRUN -> [FAIL][129] ([i915#132] / [i915#3467]) +1 similar issue [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@kms_psr@psr2_primary_mmap_gtt.html * igt@kms_psr@psr2_sprite_mmap_cpu: - shard-iclb: NOTRUN -> [SKIP][130] ([fdo#109441]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html * igt@kms_setmode@basic: - shard-apl: [PASS][131] -> [FAIL][132] ([i915#31]) [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-apl1/igt@kms_setmode@basic.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl2/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-d-wait-idle: - shard-skl: NOTRUN -> [SKIP][133] ([fdo#109271] / [i915#533]) +1 similar issue [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@kms_vblank@pipe-d-wait-idle.html * igt@kms_writeback@writeback-fb-id: - shard-kbl: NOTRUN -> [SKIP][134] ([fdo#109271] / [i915#2437]) +1 similar issue [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@kms_writeback@writeback-fb-id.html - shard-iclb: NOTRUN -> [SKIP][135] ([i915#2437]) [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@kms_writeback@writeback-fb-id.html * igt@nouveau_crc@pipe-c-source-outp-complete: - shard-tglb: NOTRUN -> [SKIP][136] ([i915#2530]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@nouveau_crc@pipe-c-source-outp-complete.html * igt@perf@polling-small-buf: - shard-skl: NOTRUN -> [FAIL][137] ([i915#1722]) [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl3/igt@perf@polling-small-buf.html * igt@prime_nv_api@i915_self_import_to_different_fd: - shard-tglb: NOTRUN -> [SKIP][138] ([fdo#109291]) [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglb2/igt@prime_nv_api@i915_self_import_to_different_fd.html * igt@prime_vgem@fence-read-hang: - shard-iclb: NOTRUN -> [SKIP][139] ([fdo#109295]) [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@prime_vgem@fence-read-hang.html * igt@sysfs_clients@fair-0: - shard-skl: NOTRUN -> [SKIP][140] ([fdo#109271] / [i915#2994]) +1 similar issue [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl4/igt@sysfs_clients@fair-0.html * igt@sysfs_clients@fair-1: - shard-iclb: NOTRUN -> [SKIP][141] ([i915#2994]) [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@sysfs_clients@fair-1.html - shard-apl: NOTRUN -> [SKIP][142] ([fdo#109271] / [i915#2994]) [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl7/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@sema-50: - shard-kbl: NOTRUN -> [SKIP][143] ([fdo#109271] / [i915#2994]) +2 similar issues [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl6/igt@sysfs_clients@sema-50.html #### Possible fixes #### * igt@gem_exec_balancer@parallel-balancer: - shard-iclb: [SKIP][144] ([i915#4525]) -> [PASS][145] +1 similar issue [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-iclb6/igt@gem_exec_balancer@parallel-balancer.html [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@gem_exec_balancer@parallel-balancer.html * igt@gem_exec_fair@basic-pace-solo@rcs0: - shard-apl: [FAIL][146] ([i915#2842]) -> [PASS][147] [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-apl3/igt@gem_exec_fair@basic-pace-solo@rcs0.html * igt@gem_exec_fair@basic-pace@vcs0: - shard-kbl: [FAIL][148] ([i915#2842]) -> [PASS][149] [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-kbl6/igt@gem_exec_fair@basic-pace@vcs0.html [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-kbl7/igt@gem_exec_fair@basic-pace@vcs0.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-glk: [FAIL][150] ([i915#2842]) -> [PASS][151] [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-glk8/igt@gem_exec_fair@basic-throttle@rcs0.html [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][152] ([i915#4939]) -> [PASS][153] [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-skl6/igt@gem_softpin@noreloc-s3.html [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-skl9/igt@gem_softpin@noreloc-s3.html * igt@i915_pm_backlight@fade_with_suspend: - shard-iclb: [INCOMPLETE][154] -> [PASS][155] [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-iclb4/igt@i915_pm_backlight@fade_with_suspend.html [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-iclb4/igt@i915_pm_backlight@fade_with_suspend.html * igt@i915_selftest@live@gt_pm: - {shard-tglu}: [DMESG-FAIL][156] ([i915#3987]) -> [PASS][157] [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11172/shard-tglu-5/igt@i915_selftest@live@gt_pm.html [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/shard-tglu-3/igt@i915_selftest@live@gt_pm.html * igt@i915 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22149/index.html [-- Attachment #2: Type: text/html, Size: 33767 bytes --] ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Intel-gfx] [RFC 0/2] Compile out integrated 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin ` (6 preceding siblings ...) 2022-02-01 17:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork @ 2022-02-02 11:51 ` Tvrtko Ursulin 7 siblings, 0 replies; 19+ messages in thread From: Tvrtko Ursulin @ 2022-02-02 11:51 UTC (permalink / raw) To: Intel-gfx; +Cc: Jani Nikula, Lucas De Marchi, Michael Cheng On 01/02/2022 11:15, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Quicky and dirty hack based on some old ideas. Thought maybe the approach might > interest the Arm port guys. But with IS_GEN_RANGE removed easy gains are not so > big so meh.. Maybe some more easy wins with IS_DISPLAY_VER but I haven't looked > into that side. > > 3884664 449681 6720 4341065 423d49 i915.ko.tip > 3599989 429034 6688 4035711 3d947f i915.ko.noigp > > Note debug kconfig so everything is inflated. Whether or not the relative gain > would change with production kconfig I am not sure. Non debug build for the record: text data bss dec hex filename 2188446 20528 2944 2211918 21c04e i915.ko.tip 1926865 17776 2944 1947585 1db7c1 i915.ko.noigpu So around ~12% of the driver eliminated as dead code with the easy and incomplete approach. Not bad considering no clean split on Gen12, gen based if-ladder are mostly untouched and no LTO. Regards, Tvrtko ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2022-02-08 20:34 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-02-01 11:15 [Intel-gfx] [RFC 0/2] Compile out integrated Tvrtko Ursulin 2022-02-01 11:15 ` [Intel-gfx] [RFC 1/2] igp kconfig Tvrtko Ursulin 2022-02-01 11:15 ` [Intel-gfx] [RFC 2/2] jsl/ehl Tvrtko Ursulin 2022-02-01 11:26 ` Jani Nikula 2022-02-01 13:17 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Compile out integrated Patchwork 2022-02-01 13:18 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-02-01 13:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-02-01 16:55 ` [Intel-gfx] [RFC 0/2] " Lucas De Marchi 2022-02-01 17:09 ` Jani Nikula 2022-02-01 17:28 ` Lucas De Marchi 2022-02-02 10:26 ` Tvrtko Ursulin 2022-02-02 11:20 ` Jani Nikula 2022-02-02 12:17 ` Tvrtko Ursulin 2022-02-02 12:41 ` Jani Nikula 2022-02-02 16:26 ` Lucas De Marchi 2022-02-08 10:31 ` Tvrtko Ursulin 2022-02-08 20:34 ` Lucas De Marchi 2022-02-01 17:37 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork 2022-02-02 11:51 ` [Intel-gfx] [RFC 0/2] " Tvrtko Ursulin
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