* [PATCH 0/2] Make macro definitions consistent in intel_reg.h
@ 2019-01-28 22:00 Aditya Swarup
2019-01-28 22:00 ` [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL Aditya Swarup
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Aditya Swarup @ 2019-01-28 22:00 UTC (permalink / raw)
To: intel-gfx
Arrange macros definitions for ICL, CNL and MG phy programming registers
semantically in order by dword, lane and port; to make it consistent.
Aditya Swarup (2):
drm/i915: Make macro definitions consistent for ICL and CNL
drm/i915: Make MG phy macros semantically consistent
drivers/gpu/drm/i915/i915_reg.h | 56 ++++++++++++++---------------
drivers/gpu/drm/i915/icl_dsi.c | 8 ++---
drivers/gpu/drm/i915/intel_ddi.c | 60 ++++++++++++++++----------------
3 files changed, 62 insertions(+), 62 deletions(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL 2019-01-28 22:00 [PATCH 0/2] Make macro definitions consistent in intel_reg.h Aditya Swarup @ 2019-01-28 22:00 ` Aditya Swarup 2019-02-12 23:58 ` Manasi Navare 2019-01-28 22:00 ` [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent Aditya Swarup ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Aditya Swarup @ 2019-01-28 22:00 UTC (permalink / raw) To: intel-gfx Macro definitions to be organized semantically based on dword, lane and port(in this order). Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 6 +++--- drivers/gpu/drm/i915/icl_dsi.c | 8 ++++---- drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++-------- 3 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1eca166d95bb..b0535073c3f0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1860,13 +1860,13 @@ enum i915_power_well_id { #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) -#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ +#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ _CNL_PORT_TX_DW4_LN0_AE))) #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) #define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) #define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) -#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) +#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) #define LOADGEN_SELECT (1 << 31) #define POST_CURSOR_1(x) ((x) << 12) #define POST_CURSOR_1_MASK (0x3F << 12) @@ -1893,7 +1893,7 @@ enum i915_power_well_id { #define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) #define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) #define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) -#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) +#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c index 73a7bee24a66..beb30d9a855c 100644 --- a/drivers/gpu/drm/i915/icl_dsi.c +++ b/drivers/gpu/drm/i915/icl_dsi.c @@ -246,13 +246,13 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) for (lane = 0; lane <= 3; lane++) { /* Bspec: must not use GRP register for write */ - tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane)); + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); tmp |= POST_CURSOR_1(0x0); tmp |= POST_CURSOR_2(0x0); tmp |= CURSOR_COEFF(0x3f); - I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp); + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); } } } @@ -390,11 +390,11 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) tmp &= ~LOADGEN_SELECT; I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); for (lane = 0; lane <= 3; lane++) { - tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane)); + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); tmp &= ~LOADGEN_SELECT; if (lane != 2) tmp |= LOADGEN_SELECT; - I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp); + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); } } diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index acd94354afc8..c6def69348a6 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2315,13 +2315,13 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, /* Program PORT_TX_DW4 */ /* We cannot write to GRP. It would overrite individual loadgen */ for (ln = 0; ln < 4; ln++) { - val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); + val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); - I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); + I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); } /* Program PORT_TX_DW5 */ @@ -2377,14 +2377,14 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); + val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); val &= ~LOADGEN_SELECT; if ((rate <= 600000 && width == 4 && ln >= 1) || (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { val |= LOADGEN_SELECT; } - I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); + I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ @@ -2446,13 +2446,13 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, /* Program PORT_TX_DW4 */ /* We cannot write to GRP. It would overwrite individual loadgen. */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK); val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); - I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); } /* Program PORT_TX_DW7 */ @@ -2503,14 +2503,14 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) */ for (ln = 0; ln <= 3; ln++) { - val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); val &= ~LOADGEN_SELECT; if ((rate <= 600000 && width == 4 && ln >= 1) || (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { val |= LOADGEN_SELECT; } - I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); } /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL 2019-01-28 22:00 ` [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL Aditya Swarup @ 2019-02-12 23:58 ` Manasi Navare 0 siblings, 0 replies; 10+ messages in thread From: Manasi Navare @ 2019-02-12 23:58 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx On Mon, Jan 28, 2019 at 02:00:11PM -0800, Aditya Swarup wrote: > Macro definitions to be organized semantically based on dword, lane and > port(in this order). > > Cc: Clint Taylor <clinton.a.taylor@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> I think you can change the commit message to say Combo PHY DDI programming related macro definitions since the next patch mentiones MG PHY macro defs. Also you should add Fixes tag with the SHA of the original patch that adds these macros. Everything else looks good to me w.r.t the changes suggested to use the arguments order as dword, lane, port. So with the above changes, Reviewed-by: Manasi Navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/i915_reg.h | 6 +++--- > drivers/gpu/drm/i915/icl_dsi.c | 8 ++++---- > drivers/gpu/drm/i915/intel_ddi.c | 16 ++++++++-------- > 3 files changed, 15 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 1eca166d95bb..b0535073c3f0 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1860,13 +1860,13 @@ enum i915_power_well_id { > #define _CNL_PORT_TX_DW4_LN1_AE 0x1624D0 > #define CNL_PORT_TX_DW4_GRP(port) _MMIO(_CNL_PORT_TX_DW_GRP(4, (port))) > #define CNL_PORT_TX_DW4_LN0(port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port))) > -#define CNL_PORT_TX_DW4_LN(port, ln) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ > +#define CNL_PORT_TX_DW4_LN(ln, port) _MMIO(_CNL_PORT_TX_DW_LN0(4, (port)) + \ > ((ln) * (_CNL_PORT_TX_DW4_LN1_AE - \ > _CNL_PORT_TX_DW4_LN0_AE))) > #define ICL_PORT_TX_DW4_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(4, port)) > #define ICL_PORT_TX_DW4_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(4, port)) > #define ICL_PORT_TX_DW4_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(4, 0, port)) > -#define ICL_PORT_TX_DW4_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) > +#define ICL_PORT_TX_DW4_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(4, ln, port)) > #define LOADGEN_SELECT (1 << 31) > #define POST_CURSOR_1(x) ((x) << 12) > #define POST_CURSOR_1_MASK (0x3F << 12) > @@ -1893,7 +1893,7 @@ enum i915_power_well_id { > #define ICL_PORT_TX_DW7_AUX(port) _MMIO(_ICL_PORT_TX_DW_AUX(7, port)) > #define ICL_PORT_TX_DW7_GRP(port) _MMIO(_ICL_PORT_TX_DW_GRP(7, port)) > #define ICL_PORT_TX_DW7_LN0(port) _MMIO(_ICL_PORT_TX_DW_LN(7, 0, port)) > -#define ICL_PORT_TX_DW7_LN(port, ln) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > +#define ICL_PORT_TX_DW7_LN(ln, port) _MMIO(_ICL_PORT_TX_DW_LN(7, ln, port)) > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) > > diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c > index 73a7bee24a66..beb30d9a855c 100644 > --- a/drivers/gpu/drm/i915/icl_dsi.c > +++ b/drivers/gpu/drm/i915/icl_dsi.c > @@ -246,13 +246,13 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder) > > for (lane = 0; lane <= 3; lane++) { > /* Bspec: must not use GRP register for write */ > - tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane)); > + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); > tmp &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > tmp |= POST_CURSOR_1(0x0); > tmp |= POST_CURSOR_2(0x0); > tmp |= CURSOR_COEFF(0x3f); > - I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp); > + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); > } > } > } > @@ -390,11 +390,11 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder) > tmp &= ~LOADGEN_SELECT; > I915_WRITE(ICL_PORT_TX_DW4_AUX(port), tmp); > for (lane = 0; lane <= 3; lane++) { > - tmp = I915_READ(ICL_PORT_TX_DW4_LN(port, lane)); > + tmp = I915_READ(ICL_PORT_TX_DW4_LN(lane, port)); > tmp &= ~LOADGEN_SELECT; > if (lane != 2) > tmp |= LOADGEN_SELECT; > - I915_WRITE(ICL_PORT_TX_DW4_LN(port, lane), tmp); > + I915_WRITE(ICL_PORT_TX_DW4_LN(lane, port), tmp); > } > } > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index acd94354afc8..c6def69348a6 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2315,13 +2315,13 @@ static void cnl_ddi_vswing_program(struct intel_encoder *encoder, > /* Program PORT_TX_DW4 */ > /* We cannot write to GRP. It would overrite individual loadgen */ > for (ln = 0; ln < 4; ln++) { > - val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); > + val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > - I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); > + I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); > } > > /* Program PORT_TX_DW5 */ > @@ -2377,14 +2377,14 @@ static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder, > * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) > */ > for (ln = 0; ln <= 3; ln++) { > - val = I915_READ(CNL_PORT_TX_DW4_LN(port, ln)); > + val = I915_READ(CNL_PORT_TX_DW4_LN(ln, port)); > val &= ~LOADGEN_SELECT; > > if ((rate <= 600000 && width == 4 && ln >= 1) || > (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { > val |= LOADGEN_SELECT; > } > - I915_WRITE(CNL_PORT_TX_DW4_LN(port, ln), val); > + I915_WRITE(CNL_PORT_TX_DW4_LN(ln, port), val); > } > > /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ > @@ -2446,13 +2446,13 @@ static void icl_ddi_combo_vswing_program(struct drm_i915_private *dev_priv, > /* Program PORT_TX_DW4 */ > /* We cannot write to GRP. It would overwrite individual loadgen. */ > for (ln = 0; ln <= 3; ln++) { > - val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); > + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); > val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | > CURSOR_COEFF_MASK); > val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1); > val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2); > val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff); > - I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); > + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); > } > > /* Program PORT_TX_DW7 */ > @@ -2503,14 +2503,14 @@ static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0) > */ > for (ln = 0; ln <= 3; ln++) { > - val = I915_READ(ICL_PORT_TX_DW4_LN(port, ln)); > + val = I915_READ(ICL_PORT_TX_DW4_LN(ln, port)); > val &= ~LOADGEN_SELECT; > > if ((rate <= 600000 && width == 4 && ln >= 1) || > (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) { > val |= LOADGEN_SELECT; > } > - I915_WRITE(ICL_PORT_TX_DW4_LN(port, ln), val); > + I915_WRITE(ICL_PORT_TX_DW4_LN(ln, port), val); > } > > /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */ > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent 2019-01-28 22:00 [PATCH 0/2] Make macro definitions consistent in intel_reg.h Aditya Swarup 2019-01-28 22:00 ` [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL Aditya Swarup @ 2019-01-28 22:00 ` Aditya Swarup 2019-02-12 23:59 ` Manasi Navare 2019-01-28 23:00 ` ✗ Fi.CI.CHECKPATCH: warning for Make macro definitions consistent in intel_reg.h Patchwork ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Aditya Swarup @ 2019-01-28 22:00 UTC (permalink / raw) To: intel-gfx Macros to be organized semantically by dword, lane and port(in this order). Cc: Clint Taylor <clinton.a.taylor@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++---------------- drivers/gpu/drm/i915/intel_ddi.c | 44 ++++++++++++++-------------- 2 files changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b0535073c3f0..da8fcdc456d2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1897,7 +1897,7 @@ enum i915_power_well_id { #define N_SCALAR(x) ((x) << 24) #define N_SCALAR_MASK (0x7F << 24) -#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \ +#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C @@ -1908,8 +1908,8 @@ enum i915_power_well_id { #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C -#define MG_TX1_LINK_PARAMS(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ +#define MG_TX1_LINK_PARAMS(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ MG_TX_LINK_PARAMS_TX1LN1_PORT1) @@ -1921,8 +1921,8 @@ enum i915_power_well_id { #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC -#define MG_TX2_LINK_PARAMS(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ +#define MG_TX2_LINK_PARAMS(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ MG_TX_LINK_PARAMS_TX2LN1_PORT1) #define CRI_USE_FS32 (1 << 5) @@ -1935,8 +1935,8 @@ enum i915_power_well_id { #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C -#define MG_TX1_PISO_READLOAD(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ +#define MG_TX1_PISO_READLOAD(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ MG_TX_PISO_READLOAD_TX1LN1_PORT1) @@ -1948,8 +1948,8 @@ enum i915_power_well_id { #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC -#define MG_TX2_PISO_READLOAD(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ +#define MG_TX2_PISO_READLOAD(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ MG_TX_PISO_READLOAD_TX2LN1_PORT1) #define CRI_CALCINIT (1 << 1) @@ -1962,8 +1962,8 @@ enum i915_power_well_id { #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 -#define MG_TX1_SWINGCTRL(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ +#define MG_TX1_SWINGCTRL(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ MG_TX_SWINGCTRL_TX1LN0_PORT2, \ MG_TX_SWINGCTRL_TX1LN1_PORT1) @@ -1975,8 +1975,8 @@ enum i915_power_well_id { #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 -#define MG_TX2_SWINGCTRL(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ +#define MG_TX2_SWINGCTRL(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ MG_TX_SWINGCTRL_TX2LN0_PORT2, \ MG_TX_SWINGCTRL_TX2LN1_PORT1) #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) @@ -1990,8 +1990,8 @@ enum i915_power_well_id { #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 -#define MG_TX1_DRVCTRL(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ +#define MG_TX1_DRVCTRL(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ MG_TX_DRVCTRL_TX1LN1_TXPORT1) @@ -2003,8 +2003,8 @@ enum i915_power_well_id { #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 -#define MG_TX2_DRVCTRL(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \ +#define MG_TX2_DRVCTRL(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ MG_TX_DRVCTRL_TX2LN0_PORT2, \ MG_TX_DRVCTRL_TX2LN1_PORT1) #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) @@ -2023,8 +2023,8 @@ enum i915_power_well_id { #define MG_CLKHUB_LN1_PORT3 0x16A79C #define MG_CLKHUB_LN0_PORT4 0x16B39C #define MG_CLKHUB_LN1_PORT4 0x16B79C -#define MG_CLKHUB(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \ +#define MG_CLKHUB(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \ MG_CLKHUB_LN0_PORT2, \ MG_CLKHUB_LN1_PORT1) #define CFG_LOW_RATE_LKREN_EN (1 << 11) @@ -2037,8 +2037,8 @@ enum i915_power_well_id { #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 -#define MG_TX1_DCC(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \ +#define MG_TX1_DCC(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \ MG_TX_DCC_TX1LN0_PORT2, \ MG_TX_DCC_TX1LN1_PORT1) #define MG_TX_DCC_TX2LN0_PORT1 0x168090 @@ -2049,8 +2049,8 @@ enum i915_power_well_id { #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 -#define MG_TX2_DCC(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \ +#define MG_TX2_DCC(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \ MG_TX_DCC_TX2LN0_PORT2, \ MG_TX_DCC_TX2LN1_PORT1) #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) @@ -2065,8 +2065,8 @@ enum i915_power_well_id { #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 -#define MG_DP_MODE(port, ln) \ - MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \ +#define MG_DP_MODE(ln, port) \ + MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \ MG_DP_MODE_LN0_ACU_PORT2, \ MG_DP_MODE_LN1_ACU_PORT1) #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c6def69348a6..32d42f2dc3d1 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -2553,33 +2553,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_LINK_PARAMS(port, ln)); + val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); val &= ~CRI_USE_FS32; - I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val); + I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val); - val = I915_READ(MG_TX2_LINK_PARAMS(port, ln)); + val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); val &= ~CRI_USE_FS32; - I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val); + I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val); } /* Program MG_TX_SWINGCTRL with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_SWINGCTRL(port, ln)); + val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( ddi_translations[level].cri_txdeemph_override_17_12); - I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val); + I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val); - val = I915_READ(MG_TX2_SWINGCTRL(port, ln)); + val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; val |= CRI_TXDEEMPH_OVERRIDE_17_12( ddi_translations[level].cri_txdeemph_override_17_12); - I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val); + I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val); } /* Program MG_TX_DRVCTRL with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_DRVCTRL(port, ln)); + val = I915_READ(MG_TX1_DRVCTRL(ln, port)); val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( @@ -2587,9 +2587,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, CRI_TXDEEMPH_OVERRIDE_11_6( ddi_translations[level].cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; - I915_WRITE(MG_TX1_DRVCTRL(port, ln), val); + I915_WRITE(MG_TX1_DRVCTRL(ln, port), val); - val = I915_READ(MG_TX2_DRVCTRL(port, ln)); + val = I915_READ(MG_TX2_DRVCTRL(ln, port)); val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | CRI_TXDEEMPH_OVERRIDE_5_0_MASK); val |= CRI_TXDEEMPH_OVERRIDE_5_0( @@ -2597,7 +2597,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, CRI_TXDEEMPH_OVERRIDE_11_6( ddi_translations[level].cri_txdeemph_override_11_6) | CRI_TXDEEMPH_OVERRIDE_EN; - I915_WRITE(MG_TX2_DRVCTRL(port, ln), val); + I915_WRITE(MG_TX2_DRVCTRL(ln, port), val); /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ } @@ -2608,17 +2608,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, * values from table for which TX1 and TX2 enabled. */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_CLKHUB(port, ln)); + val = I915_READ(MG_CLKHUB(ln, port)); if (link_clock < 300000) val |= CFG_LOW_RATE_LKREN_EN; else val &= ~CFG_LOW_RATE_LKREN_EN; - I915_WRITE(MG_CLKHUB(port, ln), val); + I915_WRITE(MG_CLKHUB(ln, port), val); } /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_DCC(port, ln)); + val = I915_READ(MG_TX1_DCC(ln, port)); val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; if (link_clock <= 500000) { val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; @@ -2626,9 +2626,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val |= CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); } - I915_WRITE(MG_TX1_DCC(port, ln), val); + I915_WRITE(MG_TX1_DCC(ln, port), val); - val = I915_READ(MG_TX2_DCC(port, ln)); + val = I915_READ(MG_TX2_DCC(ln, port)); val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; if (link_clock <= 500000) { val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; @@ -2636,18 +2636,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, val |= CFG_AMI_CK_DIV_OVERRIDE_EN | CFG_AMI_CK_DIV_OVERRIDE_VAL(1); } - I915_WRITE(MG_TX2_DCC(port, ln), val); + I915_WRITE(MG_TX2_DCC(ln, port), val); } /* Program MG_TX_PISO_READLOAD with values from vswing table */ for (ln = 0; ln < 2; ln++) { - val = I915_READ(MG_TX1_PISO_READLOAD(port, ln)); + val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); val |= CRI_CALCINIT; - I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val); + I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val); - val = I915_READ(MG_TX2_PISO_READLOAD(port, ln)); + val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); val |= CRI_CALCINIT; - I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val); + I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val); } } -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent 2019-01-28 22:00 ` [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent Aditya Swarup @ 2019-02-12 23:59 ` Manasi Navare 2019-02-14 7:47 ` Lucas De Marchi 0 siblings, 1 reply; 10+ messages in thread From: Manasi Navare @ 2019-02-12 23:59 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx On Mon, Jan 28, 2019 at 02:00:12PM -0800, Aditya Swarup wrote: > Macros to be organized semantically by dword, lane and > port(in this order). > > Cc: Clint Taylor <clinton.a.taylor@intel.com> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Jani Nikula <jani.nikula@linux.intel.com> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Also please add Fixes tag with SHA of the original patch that adds these macros. With that, Reviewed-by: Manasi navare <manasi.d.navare@intel.com> Manasi > --- > drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++---------------- > drivers/gpu/drm/i915/intel_ddi.c | 44 ++++++++++++++-------------- > 2 files changed, 47 insertions(+), 47 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b0535073c3f0..da8fcdc456d2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1897,7 +1897,7 @@ enum i915_power_well_id { > #define N_SCALAR(x) ((x) << 24) > #define N_SCALAR_MASK (0x7F << 24) > > -#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \ > +#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) > > #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C > @@ -1908,8 +1908,8 @@ enum i915_power_well_id { > #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C > #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C > #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C > -#define MG_TX1_LINK_PARAMS(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ > +#define MG_TX1_LINK_PARAMS(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ > MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ > MG_TX_LINK_PARAMS_TX1LN1_PORT1) > > @@ -1921,8 +1921,8 @@ enum i915_power_well_id { > #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC > #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC > #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC > -#define MG_TX2_LINK_PARAMS(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ > +#define MG_TX2_LINK_PARAMS(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ > MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ > MG_TX_LINK_PARAMS_TX2LN1_PORT1) > #define CRI_USE_FS32 (1 << 5) > @@ -1935,8 +1935,8 @@ enum i915_power_well_id { > #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C > #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C > #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C > -#define MG_TX1_PISO_READLOAD(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ > +#define MG_TX1_PISO_READLOAD(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ > MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ > MG_TX_PISO_READLOAD_TX1LN1_PORT1) > > @@ -1948,8 +1948,8 @@ enum i915_power_well_id { > #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC > #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC > #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC > -#define MG_TX2_PISO_READLOAD(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ > +#define MG_TX2_PISO_READLOAD(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ > MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ > MG_TX_PISO_READLOAD_TX2LN1_PORT1) > #define CRI_CALCINIT (1 << 1) > @@ -1962,8 +1962,8 @@ enum i915_power_well_id { > #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 > #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 > #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 > -#define MG_TX1_SWINGCTRL(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ > +#define MG_TX1_SWINGCTRL(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ > MG_TX_SWINGCTRL_TX1LN0_PORT2, \ > MG_TX_SWINGCTRL_TX1LN1_PORT1) > > @@ -1975,8 +1975,8 @@ enum i915_power_well_id { > #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 > #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 > #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 > -#define MG_TX2_SWINGCTRL(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ > +#define MG_TX2_SWINGCTRL(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ > MG_TX_SWINGCTRL_TX2LN0_PORT2, \ > MG_TX_SWINGCTRL_TX2LN1_PORT1) > #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) > @@ -1990,8 +1990,8 @@ enum i915_power_well_id { > #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 > #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 > #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 > -#define MG_TX1_DRVCTRL(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ > +#define MG_TX1_DRVCTRL(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ > MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ > MG_TX_DRVCTRL_TX1LN1_TXPORT1) > > @@ -2003,8 +2003,8 @@ enum i915_power_well_id { > #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 > #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 > #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 > -#define MG_TX2_DRVCTRL(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \ > +#define MG_TX2_DRVCTRL(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ > MG_TX_DRVCTRL_TX2LN0_PORT2, \ > MG_TX_DRVCTRL_TX2LN1_PORT1) > #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) > @@ -2023,8 +2023,8 @@ enum i915_power_well_id { > #define MG_CLKHUB_LN1_PORT3 0x16A79C > #define MG_CLKHUB_LN0_PORT4 0x16B39C > #define MG_CLKHUB_LN1_PORT4 0x16B79C > -#define MG_CLKHUB(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \ > +#define MG_CLKHUB(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \ > MG_CLKHUB_LN0_PORT2, \ > MG_CLKHUB_LN1_PORT1) > #define CFG_LOW_RATE_LKREN_EN (1 << 11) > @@ -2037,8 +2037,8 @@ enum i915_power_well_id { > #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 > #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 > #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 > -#define MG_TX1_DCC(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \ > +#define MG_TX1_DCC(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \ > MG_TX_DCC_TX1LN0_PORT2, \ > MG_TX_DCC_TX1LN1_PORT1) > #define MG_TX_DCC_TX2LN0_PORT1 0x168090 > @@ -2049,8 +2049,8 @@ enum i915_power_well_id { > #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 > #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 > #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 > -#define MG_TX2_DCC(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \ > +#define MG_TX2_DCC(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \ > MG_TX_DCC_TX2LN0_PORT2, \ > MG_TX_DCC_TX2LN1_PORT1) > #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) > @@ -2065,8 +2065,8 @@ enum i915_power_well_id { > #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 > #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 > #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 > -#define MG_DP_MODE(port, ln) \ > - MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \ > +#define MG_DP_MODE(ln, port) \ > + MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \ > MG_DP_MODE_LN0_ACU_PORT2, \ > MG_DP_MODE_LN1_ACU_PORT1) > #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > index c6def69348a6..32d42f2dc3d1 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -2553,33 +2553,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ > for (ln = 0; ln < 2; ln++) { > - val = I915_READ(MG_TX1_LINK_PARAMS(port, ln)); > + val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); > val &= ~CRI_USE_FS32; > - I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val); > + I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val); > > - val = I915_READ(MG_TX2_LINK_PARAMS(port, ln)); > + val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); > val &= ~CRI_USE_FS32; > - I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val); > + I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val); > } > > /* Program MG_TX_SWINGCTRL with values from vswing table */ > for (ln = 0; ln < 2; ln++) { > - val = I915_READ(MG_TX1_SWINGCTRL(port, ln)); > + val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; > val |= CRI_TXDEEMPH_OVERRIDE_17_12( > ddi_translations[level].cri_txdeemph_override_17_12); > - I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val); > + I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val); > > - val = I915_READ(MG_TX2_SWINGCTRL(port, ln)); > + val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; > val |= CRI_TXDEEMPH_OVERRIDE_17_12( > ddi_translations[level].cri_txdeemph_override_17_12); > - I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val); > + I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val); > } > > /* Program MG_TX_DRVCTRL with values from vswing table */ > for (ln = 0; ln < 2; ln++) { > - val = I915_READ(MG_TX1_DRVCTRL(port, ln)); > + val = I915_READ(MG_TX1_DRVCTRL(ln, port)); > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); > val |= CRI_TXDEEMPH_OVERRIDE_5_0( > @@ -2587,9 +2587,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > CRI_TXDEEMPH_OVERRIDE_11_6( > ddi_translations[level].cri_txdeemph_override_11_6) | > CRI_TXDEEMPH_OVERRIDE_EN; > - I915_WRITE(MG_TX1_DRVCTRL(port, ln), val); > + I915_WRITE(MG_TX1_DRVCTRL(ln, port), val); > > - val = I915_READ(MG_TX2_DRVCTRL(port, ln)); > + val = I915_READ(MG_TX2_DRVCTRL(ln, port)); > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); > val |= CRI_TXDEEMPH_OVERRIDE_5_0( > @@ -2597,7 +2597,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > CRI_TXDEEMPH_OVERRIDE_11_6( > ddi_translations[level].cri_txdeemph_override_11_6) | > CRI_TXDEEMPH_OVERRIDE_EN; > - I915_WRITE(MG_TX2_DRVCTRL(port, ln), val); > + I915_WRITE(MG_TX2_DRVCTRL(ln, port), val); > > /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ > } > @@ -2608,17 +2608,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > * values from table for which TX1 and TX2 enabled. > */ > for (ln = 0; ln < 2; ln++) { > - val = I915_READ(MG_CLKHUB(port, ln)); > + val = I915_READ(MG_CLKHUB(ln, port)); > if (link_clock < 300000) > val |= CFG_LOW_RATE_LKREN_EN; > else > val &= ~CFG_LOW_RATE_LKREN_EN; > - I915_WRITE(MG_CLKHUB(port, ln), val); > + I915_WRITE(MG_CLKHUB(ln, port), val); > } > > /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ > for (ln = 0; ln < 2; ln++) { > - val = I915_READ(MG_TX1_DCC(port, ln)); > + val = I915_READ(MG_TX1_DCC(ln, port)); > val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; > if (link_clock <= 500000) { > val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; > @@ -2626,9 +2626,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > val |= CFG_AMI_CK_DIV_OVERRIDE_EN | > CFG_AMI_CK_DIV_OVERRIDE_VAL(1); > } > - I915_WRITE(MG_TX1_DCC(port, ln), val); > + I915_WRITE(MG_TX1_DCC(ln, port), val); > > - val = I915_READ(MG_TX2_DCC(port, ln)); > + val = I915_READ(MG_TX2_DCC(ln, port)); > val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; > if (link_clock <= 500000) { > val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; > @@ -2636,18 +2636,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > val |= CFG_AMI_CK_DIV_OVERRIDE_EN | > CFG_AMI_CK_DIV_OVERRIDE_VAL(1); > } > - I915_WRITE(MG_TX2_DCC(port, ln), val); > + I915_WRITE(MG_TX2_DCC(ln, port), val); > } > > /* Program MG_TX_PISO_READLOAD with values from vswing table */ > for (ln = 0; ln < 2; ln++) { > - val = I915_READ(MG_TX1_PISO_READLOAD(port, ln)); > + val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); > val |= CRI_CALCINIT; > - I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val); > + I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val); > > - val = I915_READ(MG_TX2_PISO_READLOAD(port, ln)); > + val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); > val |= CRI_CALCINIT; > - I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val); > + I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val); > } > } > > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent 2019-02-12 23:59 ` Manasi Navare @ 2019-02-14 7:47 ` Lucas De Marchi 2019-02-14 13:39 ` Jani Nikula 0 siblings, 1 reply; 10+ messages in thread From: Lucas De Marchi @ 2019-02-14 7:47 UTC (permalink / raw) To: Manasi Navare; +Cc: Intel Graphics On Tue, Feb 12, 2019 at 3:57 PM Manasi Navare <manasi.d.navare@intel.com> wrote: > > On Mon, Jan 28, 2019 at 02:00:12PM -0800, Aditya Swarup wrote: > > Macros to be organized semantically by dword, lane and > > port(in this order). > > > > Cc: Clint Taylor <clinton.a.taylor@intel.com> > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: Jani Nikula <jani.nikula@linux.intel.com> > > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> > > Also please add Fixes tag with SHA of the original patch that > adds these macros. but this doesn't fix a bug, does it? why would you propagate this to stable? Lucas De Marchi > With that, > > Reviewed-by: Manasi navare <manasi.d.navare@intel.com> > > Manasi > > > --- > > drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++---------------- > > drivers/gpu/drm/i915/intel_ddi.c | 44 ++++++++++++++-------------- > > 2 files changed, 47 insertions(+), 47 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index b0535073c3f0..da8fcdc456d2 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -1897,7 +1897,7 @@ enum i915_power_well_id { > > #define N_SCALAR(x) ((x) << 24) > > #define N_SCALAR_MASK (0x7F << 24) > > > > -#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \ > > +#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ > > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) > > > > #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C > > @@ -1908,8 +1908,8 @@ enum i915_power_well_id { > > #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C > > #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C > > #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C > > -#define MG_TX1_LINK_PARAMS(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ > > +#define MG_TX1_LINK_PARAMS(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ > > MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ > > MG_TX_LINK_PARAMS_TX1LN1_PORT1) > > > > @@ -1921,8 +1921,8 @@ enum i915_power_well_id { > > #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC > > #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC > > #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC > > -#define MG_TX2_LINK_PARAMS(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ > > +#define MG_TX2_LINK_PARAMS(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ > > MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ > > MG_TX_LINK_PARAMS_TX2LN1_PORT1) > > #define CRI_USE_FS32 (1 << 5) > > @@ -1935,8 +1935,8 @@ enum i915_power_well_id { > > #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C > > #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C > > #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C > > -#define MG_TX1_PISO_READLOAD(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ > > +#define MG_TX1_PISO_READLOAD(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ > > MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ > > MG_TX_PISO_READLOAD_TX1LN1_PORT1) > > > > @@ -1948,8 +1948,8 @@ enum i915_power_well_id { > > #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC > > #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC > > #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC > > -#define MG_TX2_PISO_READLOAD(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ > > +#define MG_TX2_PISO_READLOAD(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ > > MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ > > MG_TX_PISO_READLOAD_TX2LN1_PORT1) > > #define CRI_CALCINIT (1 << 1) > > @@ -1962,8 +1962,8 @@ enum i915_power_well_id { > > #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 > > #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 > > #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 > > -#define MG_TX1_SWINGCTRL(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ > > +#define MG_TX1_SWINGCTRL(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ > > MG_TX_SWINGCTRL_TX1LN0_PORT2, \ > > MG_TX_SWINGCTRL_TX1LN1_PORT1) > > > > @@ -1975,8 +1975,8 @@ enum i915_power_well_id { > > #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 > > #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 > > #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 > > -#define MG_TX2_SWINGCTRL(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ > > +#define MG_TX2_SWINGCTRL(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ > > MG_TX_SWINGCTRL_TX2LN0_PORT2, \ > > MG_TX_SWINGCTRL_TX2LN1_PORT1) > > #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) > > @@ -1990,8 +1990,8 @@ enum i915_power_well_id { > > #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 > > #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 > > #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 > > -#define MG_TX1_DRVCTRL(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ > > +#define MG_TX1_DRVCTRL(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ > > MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ > > MG_TX_DRVCTRL_TX1LN1_TXPORT1) > > > > @@ -2003,8 +2003,8 @@ enum i915_power_well_id { > > #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 > > #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 > > #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 > > -#define MG_TX2_DRVCTRL(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \ > > +#define MG_TX2_DRVCTRL(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ > > MG_TX_DRVCTRL_TX2LN0_PORT2, \ > > MG_TX_DRVCTRL_TX2LN1_PORT1) > > #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) > > @@ -2023,8 +2023,8 @@ enum i915_power_well_id { > > #define MG_CLKHUB_LN1_PORT3 0x16A79C > > #define MG_CLKHUB_LN0_PORT4 0x16B39C > > #define MG_CLKHUB_LN1_PORT4 0x16B79C > > -#define MG_CLKHUB(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \ > > +#define MG_CLKHUB(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \ > > MG_CLKHUB_LN0_PORT2, \ > > MG_CLKHUB_LN1_PORT1) > > #define CFG_LOW_RATE_LKREN_EN (1 << 11) > > @@ -2037,8 +2037,8 @@ enum i915_power_well_id { > > #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 > > #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 > > #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 > > -#define MG_TX1_DCC(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \ > > +#define MG_TX1_DCC(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \ > > MG_TX_DCC_TX1LN0_PORT2, \ > > MG_TX_DCC_TX1LN1_PORT1) > > #define MG_TX_DCC_TX2LN0_PORT1 0x168090 > > @@ -2049,8 +2049,8 @@ enum i915_power_well_id { > > #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 > > #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 > > #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 > > -#define MG_TX2_DCC(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \ > > +#define MG_TX2_DCC(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \ > > MG_TX_DCC_TX2LN0_PORT2, \ > > MG_TX_DCC_TX2LN1_PORT1) > > #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) > > @@ -2065,8 +2065,8 @@ enum i915_power_well_id { > > #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 > > #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 > > #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 > > -#define MG_DP_MODE(port, ln) \ > > - MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \ > > +#define MG_DP_MODE(ln, port) \ > > + MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \ > > MG_DP_MODE_LN0_ACU_PORT2, \ > > MG_DP_MODE_LN1_ACU_PORT1) > > #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c > > index c6def69348a6..32d42f2dc3d1 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -2553,33 +2553,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > > > /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ > > for (ln = 0; ln < 2; ln++) { > > - val = I915_READ(MG_TX1_LINK_PARAMS(port, ln)); > > + val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); > > val &= ~CRI_USE_FS32; > > - I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val); > > + I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val); > > > > - val = I915_READ(MG_TX2_LINK_PARAMS(port, ln)); > > + val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); > > val &= ~CRI_USE_FS32; > > - I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val); > > + I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val); > > } > > > > /* Program MG_TX_SWINGCTRL with values from vswing table */ > > for (ln = 0; ln < 2; ln++) { > > - val = I915_READ(MG_TX1_SWINGCTRL(port, ln)); > > + val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); > > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; > > val |= CRI_TXDEEMPH_OVERRIDE_17_12( > > ddi_translations[level].cri_txdeemph_override_17_12); > > - I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val); > > + I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val); > > > > - val = I915_READ(MG_TX2_SWINGCTRL(port, ln)); > > + val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); > > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; > > val |= CRI_TXDEEMPH_OVERRIDE_17_12( > > ddi_translations[level].cri_txdeemph_override_17_12); > > - I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val); > > + I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val); > > } > > > > /* Program MG_TX_DRVCTRL with values from vswing table */ > > for (ln = 0; ln < 2; ln++) { > > - val = I915_READ(MG_TX1_DRVCTRL(port, ln)); > > + val = I915_READ(MG_TX1_DRVCTRL(ln, port)); > > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | > > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); > > val |= CRI_TXDEEMPH_OVERRIDE_5_0( > > @@ -2587,9 +2587,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > CRI_TXDEEMPH_OVERRIDE_11_6( > > ddi_translations[level].cri_txdeemph_override_11_6) | > > CRI_TXDEEMPH_OVERRIDE_EN; > > - I915_WRITE(MG_TX1_DRVCTRL(port, ln), val); > > + I915_WRITE(MG_TX1_DRVCTRL(ln, port), val); > > > > - val = I915_READ(MG_TX2_DRVCTRL(port, ln)); > > + val = I915_READ(MG_TX2_DRVCTRL(ln, port)); > > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | > > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); > > val |= CRI_TXDEEMPH_OVERRIDE_5_0( > > @@ -2597,7 +2597,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > CRI_TXDEEMPH_OVERRIDE_11_6( > > ddi_translations[level].cri_txdeemph_override_11_6) | > > CRI_TXDEEMPH_OVERRIDE_EN; > > - I915_WRITE(MG_TX2_DRVCTRL(port, ln), val); > > + I915_WRITE(MG_TX2_DRVCTRL(ln, port), val); > > > > /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ > > } > > @@ -2608,17 +2608,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > * values from table for which TX1 and TX2 enabled. > > */ > > for (ln = 0; ln < 2; ln++) { > > - val = I915_READ(MG_CLKHUB(port, ln)); > > + val = I915_READ(MG_CLKHUB(ln, port)); > > if (link_clock < 300000) > > val |= CFG_LOW_RATE_LKREN_EN; > > else > > val &= ~CFG_LOW_RATE_LKREN_EN; > > - I915_WRITE(MG_CLKHUB(port, ln), val); > > + I915_WRITE(MG_CLKHUB(ln, port), val); > > } > > > > /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ > > for (ln = 0; ln < 2; ln++) { > > - val = I915_READ(MG_TX1_DCC(port, ln)); > > + val = I915_READ(MG_TX1_DCC(ln, port)); > > val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; > > if (link_clock <= 500000) { > > val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; > > @@ -2626,9 +2626,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > val |= CFG_AMI_CK_DIV_OVERRIDE_EN | > > CFG_AMI_CK_DIV_OVERRIDE_VAL(1); > > } > > - I915_WRITE(MG_TX1_DCC(port, ln), val); > > + I915_WRITE(MG_TX1_DCC(ln, port), val); > > > > - val = I915_READ(MG_TX2_DCC(port, ln)); > > + val = I915_READ(MG_TX2_DCC(ln, port)); > > val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; > > if (link_clock <= 500000) { > > val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; > > @@ -2636,18 +2636,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, > > val |= CFG_AMI_CK_DIV_OVERRIDE_EN | > > CFG_AMI_CK_DIV_OVERRIDE_VAL(1); > > } > > - I915_WRITE(MG_TX2_DCC(port, ln), val); > > + I915_WRITE(MG_TX2_DCC(ln, port), val); > > } > > > > /* Program MG_TX_PISO_READLOAD with values from vswing table */ > > for (ln = 0; ln < 2; ln++) { > > - val = I915_READ(MG_TX1_PISO_READLOAD(port, ln)); > > + val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); > > val |= CRI_CALCINIT; > > - I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val); > > + I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val); > > > > - val = I915_READ(MG_TX2_PISO_READLOAD(port, ln)); > > + val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); > > val |= CRI_CALCINIT; > > - I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val); > > + I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val); > > } > > } > > > > -- > > 2.17.1 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Lucas De Marchi _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent 2019-02-14 7:47 ` Lucas De Marchi @ 2019-02-14 13:39 ` Jani Nikula 0 siblings, 0 replies; 10+ messages in thread From: Jani Nikula @ 2019-02-14 13:39 UTC (permalink / raw) To: Lucas De Marchi, Manasi Navare; +Cc: Intel Graphics On Wed, 13 Feb 2019, Lucas De Marchi <lucas.de.marchi@gmail.com> wrote: > On Tue, Feb 12, 2019 at 3:57 PM Manasi Navare <manasi.d.navare@intel.com> wrote: >> >> On Mon, Jan 28, 2019 at 02:00:12PM -0800, Aditya Swarup wrote: >> > Macros to be organized semantically by dword, lane and >> > port(in this order). >> > >> > Cc: Clint Taylor <clinton.a.taylor@intel.com> >> > Cc: Imre Deak <imre.deak@intel.com> >> > Cc: Jani Nikula <jani.nikula@linux.intel.com> >> > Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> >> >> Also please add Fixes tag with SHA of the original patch that >> adds these macros. > > but this doesn't fix a bug, does it? why would you propagate this to stable? Thanks for the patches and review. Pushed with the commit messages updated, but without fixes tags. We don't want these to propagate to stable. BR, Jani. > > Lucas De Marchi > >> With that, >> >> Reviewed-by: Manasi navare <manasi.d.navare@intel.com> >> >> Manasi >> >> > --- >> > drivers/gpu/drm/i915/i915_reg.h | 50 ++++++++++++++++---------------- >> > drivers/gpu/drm/i915/intel_ddi.c | 44 ++++++++++++++-------------- >> > 2 files changed, 47 insertions(+), 47 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h >> > index b0535073c3f0..da8fcdc456d2 100644 >> > --- a/drivers/gpu/drm/i915/i915_reg.h >> > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > @@ -1897,7 +1897,7 @@ enum i915_power_well_id { >> > #define N_SCALAR(x) ((x) << 24) >> > #define N_SCALAR_MASK (0x7F << 24) >> > >> > -#define MG_PHY_PORT_LN(port, ln, ln0p1, ln0p2, ln1p1) \ >> > +#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ >> > _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) >> > >> > #define MG_TX_LINK_PARAMS_TX1LN0_PORT1 0x16812C >> > @@ -1908,8 +1908,8 @@ enum i915_power_well_id { >> > #define MG_TX_LINK_PARAMS_TX1LN1_PORT3 0x16A52C >> > #define MG_TX_LINK_PARAMS_TX1LN0_PORT4 0x16B12C >> > #define MG_TX_LINK_PARAMS_TX1LN1_PORT4 0x16B52C >> > -#define MG_TX1_LINK_PARAMS(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ >> > +#define MG_TX1_LINK_PARAMS(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX1LN0_PORT1, \ >> > MG_TX_LINK_PARAMS_TX1LN0_PORT2, \ >> > MG_TX_LINK_PARAMS_TX1LN1_PORT1) >> > >> > @@ -1921,8 +1921,8 @@ enum i915_power_well_id { >> > #define MG_TX_LINK_PARAMS_TX2LN1_PORT3 0x16A4AC >> > #define MG_TX_LINK_PARAMS_TX2LN0_PORT4 0x16B0AC >> > #define MG_TX_LINK_PARAMS_TX2LN1_PORT4 0x16B4AC >> > -#define MG_TX2_LINK_PARAMS(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ >> > +#define MG_TX2_LINK_PARAMS(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_LINK_PARAMS_TX2LN0_PORT1, \ >> > MG_TX_LINK_PARAMS_TX2LN0_PORT2, \ >> > MG_TX_LINK_PARAMS_TX2LN1_PORT1) >> > #define CRI_USE_FS32 (1 << 5) >> > @@ -1935,8 +1935,8 @@ enum i915_power_well_id { >> > #define MG_TX_PISO_READLOAD_TX1LN1_PORT3 0x16A54C >> > #define MG_TX_PISO_READLOAD_TX1LN0_PORT4 0x16B14C >> > #define MG_TX_PISO_READLOAD_TX1LN1_PORT4 0x16B54C >> > -#define MG_TX1_PISO_READLOAD(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ >> > +#define MG_TX1_PISO_READLOAD(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX1LN0_PORT1, \ >> > MG_TX_PISO_READLOAD_TX1LN0_PORT2, \ >> > MG_TX_PISO_READLOAD_TX1LN1_PORT1) >> > >> > @@ -1948,8 +1948,8 @@ enum i915_power_well_id { >> > #define MG_TX_PISO_READLOAD_TX2LN1_PORT3 0x16A4CC >> > #define MG_TX_PISO_READLOAD_TX2LN0_PORT4 0x16B0CC >> > #define MG_TX_PISO_READLOAD_TX2LN1_PORT4 0x16B4CC >> > -#define MG_TX2_PISO_READLOAD(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ >> > +#define MG_TX2_PISO_READLOAD(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_PISO_READLOAD_TX2LN0_PORT1, \ >> > MG_TX_PISO_READLOAD_TX2LN0_PORT2, \ >> > MG_TX_PISO_READLOAD_TX2LN1_PORT1) >> > #define CRI_CALCINIT (1 << 1) >> > @@ -1962,8 +1962,8 @@ enum i915_power_well_id { >> > #define MG_TX_SWINGCTRL_TX1LN1_PORT3 0x16A548 >> > #define MG_TX_SWINGCTRL_TX1LN0_PORT4 0x16B148 >> > #define MG_TX_SWINGCTRL_TX1LN1_PORT4 0x16B548 >> > -#define MG_TX1_SWINGCTRL(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ >> > +#define MG_TX1_SWINGCTRL(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX1LN0_PORT1, \ >> > MG_TX_SWINGCTRL_TX1LN0_PORT2, \ >> > MG_TX_SWINGCTRL_TX1LN1_PORT1) >> > >> > @@ -1975,8 +1975,8 @@ enum i915_power_well_id { >> > #define MG_TX_SWINGCTRL_TX2LN1_PORT3 0x16A4C8 >> > #define MG_TX_SWINGCTRL_TX2LN0_PORT4 0x16B0C8 >> > #define MG_TX_SWINGCTRL_TX2LN1_PORT4 0x16B4C8 >> > -#define MG_TX2_SWINGCTRL(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ >> > +#define MG_TX2_SWINGCTRL(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_SWINGCTRL_TX2LN0_PORT1, \ >> > MG_TX_SWINGCTRL_TX2LN0_PORT2, \ >> > MG_TX_SWINGCTRL_TX2LN1_PORT1) >> > #define CRI_TXDEEMPH_OVERRIDE_17_12(x) ((x) << 0) >> > @@ -1990,8 +1990,8 @@ enum i915_power_well_id { >> > #define MG_TX_DRVCTRL_TX1LN1_TXPORT3 0x16A544 >> > #define MG_TX_DRVCTRL_TX1LN0_TXPORT4 0x16B144 >> > #define MG_TX_DRVCTRL_TX1LN1_TXPORT4 0x16B544 >> > -#define MG_TX1_DRVCTRL(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ >> > +#define MG_TX1_DRVCTRL(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX1LN0_TXPORT1, \ >> > MG_TX_DRVCTRL_TX1LN0_TXPORT2, \ >> > MG_TX_DRVCTRL_TX1LN1_TXPORT1) >> > >> > @@ -2003,8 +2003,8 @@ enum i915_power_well_id { >> > #define MG_TX_DRVCTRL_TX2LN1_PORT3 0x16A4C4 >> > #define MG_TX_DRVCTRL_TX2LN0_PORT4 0x16B0C4 >> > #define MG_TX_DRVCTRL_TX2LN1_PORT4 0x16B4C4 >> > -#define MG_TX2_DRVCTRL(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_DRVCTRL_TX2LN0_PORT1, \ >> > +#define MG_TX2_DRVCTRL(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_DRVCTRL_TX2LN0_PORT1, \ >> > MG_TX_DRVCTRL_TX2LN0_PORT2, \ >> > MG_TX_DRVCTRL_TX2LN1_PORT1) >> > #define CRI_TXDEEMPH_OVERRIDE_11_6(x) ((x) << 24) >> > @@ -2023,8 +2023,8 @@ enum i915_power_well_id { >> > #define MG_CLKHUB_LN1_PORT3 0x16A79C >> > #define MG_CLKHUB_LN0_PORT4 0x16B39C >> > #define MG_CLKHUB_LN1_PORT4 0x16B79C >> > -#define MG_CLKHUB(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_CLKHUB_LN0_PORT1, \ >> > +#define MG_CLKHUB(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_CLKHUB_LN0_PORT1, \ >> > MG_CLKHUB_LN0_PORT2, \ >> > MG_CLKHUB_LN1_PORT1) >> > #define CFG_LOW_RATE_LKREN_EN (1 << 11) >> > @@ -2037,8 +2037,8 @@ enum i915_power_well_id { >> > #define MG_TX_DCC_TX1LN1_PORT3 0x16A510 >> > #define MG_TX_DCC_TX1LN0_PORT4 0x16B110 >> > #define MG_TX_DCC_TX1LN1_PORT4 0x16B510 >> > -#define MG_TX1_DCC(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX1LN0_PORT1, \ >> > +#define MG_TX1_DCC(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX1LN0_PORT1, \ >> > MG_TX_DCC_TX1LN0_PORT2, \ >> > MG_TX_DCC_TX1LN1_PORT1) >> > #define MG_TX_DCC_TX2LN0_PORT1 0x168090 >> > @@ -2049,8 +2049,8 @@ enum i915_power_well_id { >> > #define MG_TX_DCC_TX2LN1_PORT3 0x16A490 >> > #define MG_TX_DCC_TX2LN0_PORT4 0x16B090 >> > #define MG_TX_DCC_TX2LN1_PORT4 0x16B490 >> > -#define MG_TX2_DCC(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_TX_DCC_TX2LN0_PORT1, \ >> > +#define MG_TX2_DCC(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_TX_DCC_TX2LN0_PORT1, \ >> > MG_TX_DCC_TX2LN0_PORT2, \ >> > MG_TX_DCC_TX2LN1_PORT1) >> > #define CFG_AMI_CK_DIV_OVERRIDE_VAL(x) ((x) << 25) >> > @@ -2065,8 +2065,8 @@ enum i915_power_well_id { >> > #define MG_DP_MODE_LN1_ACU_PORT3 0x16A7A0 >> > #define MG_DP_MODE_LN0_ACU_PORT4 0x16B3A0 >> > #define MG_DP_MODE_LN1_ACU_PORT4 0x16B7A0 >> > -#define MG_DP_MODE(port, ln) \ >> > - MG_PHY_PORT_LN(port, ln, MG_DP_MODE_LN0_ACU_PORT1, \ >> > +#define MG_DP_MODE(ln, port) \ >> > + MG_PHY_PORT_LN(ln, port, MG_DP_MODE_LN0_ACU_PORT1, \ >> > MG_DP_MODE_LN0_ACU_PORT2, \ >> > MG_DP_MODE_LN1_ACU_PORT1) >> > #define MG_DP_MODE_CFG_DP_X2_MODE (1 << 7) >> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c >> > index c6def69348a6..32d42f2dc3d1 100644 >> > --- a/drivers/gpu/drm/i915/intel_ddi.c >> > +++ b/drivers/gpu/drm/i915/intel_ddi.c >> > @@ -2553,33 +2553,33 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> > >> > /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */ >> > for (ln = 0; ln < 2; ln++) { >> > - val = I915_READ(MG_TX1_LINK_PARAMS(port, ln)); >> > + val = I915_READ(MG_TX1_LINK_PARAMS(ln, port)); >> > val &= ~CRI_USE_FS32; >> > - I915_WRITE(MG_TX1_LINK_PARAMS(port, ln), val); >> > + I915_WRITE(MG_TX1_LINK_PARAMS(ln, port), val); >> > >> > - val = I915_READ(MG_TX2_LINK_PARAMS(port, ln)); >> > + val = I915_READ(MG_TX2_LINK_PARAMS(ln, port)); >> > val &= ~CRI_USE_FS32; >> > - I915_WRITE(MG_TX2_LINK_PARAMS(port, ln), val); >> > + I915_WRITE(MG_TX2_LINK_PARAMS(ln, port), val); >> > } >> > >> > /* Program MG_TX_SWINGCTRL with values from vswing table */ >> > for (ln = 0; ln < 2; ln++) { >> > - val = I915_READ(MG_TX1_SWINGCTRL(port, ln)); >> > + val = I915_READ(MG_TX1_SWINGCTRL(ln, port)); >> > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; >> > val |= CRI_TXDEEMPH_OVERRIDE_17_12( >> > ddi_translations[level].cri_txdeemph_override_17_12); >> > - I915_WRITE(MG_TX1_SWINGCTRL(port, ln), val); >> > + I915_WRITE(MG_TX1_SWINGCTRL(ln, port), val); >> > >> > - val = I915_READ(MG_TX2_SWINGCTRL(port, ln)); >> > + val = I915_READ(MG_TX2_SWINGCTRL(ln, port)); >> > val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK; >> > val |= CRI_TXDEEMPH_OVERRIDE_17_12( >> > ddi_translations[level].cri_txdeemph_override_17_12); >> > - I915_WRITE(MG_TX2_SWINGCTRL(port, ln), val); >> > + I915_WRITE(MG_TX2_SWINGCTRL(ln, port), val); >> > } >> > >> > /* Program MG_TX_DRVCTRL with values from vswing table */ >> > for (ln = 0; ln < 2; ln++) { >> > - val = I915_READ(MG_TX1_DRVCTRL(port, ln)); >> > + val = I915_READ(MG_TX1_DRVCTRL(ln, port)); >> > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | >> > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); >> > val |= CRI_TXDEEMPH_OVERRIDE_5_0( >> > @@ -2587,9 +2587,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> > CRI_TXDEEMPH_OVERRIDE_11_6( >> > ddi_translations[level].cri_txdeemph_override_11_6) | >> > CRI_TXDEEMPH_OVERRIDE_EN; >> > - I915_WRITE(MG_TX1_DRVCTRL(port, ln), val); >> > + I915_WRITE(MG_TX1_DRVCTRL(ln, port), val); >> > >> > - val = I915_READ(MG_TX2_DRVCTRL(port, ln)); >> > + val = I915_READ(MG_TX2_DRVCTRL(ln, port)); >> > val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK | >> > CRI_TXDEEMPH_OVERRIDE_5_0_MASK); >> > val |= CRI_TXDEEMPH_OVERRIDE_5_0( >> > @@ -2597,7 +2597,7 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> > CRI_TXDEEMPH_OVERRIDE_11_6( >> > ddi_translations[level].cri_txdeemph_override_11_6) | >> > CRI_TXDEEMPH_OVERRIDE_EN; >> > - I915_WRITE(MG_TX2_DRVCTRL(port, ln), val); >> > + I915_WRITE(MG_TX2_DRVCTRL(ln, port), val); >> > >> > /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */ >> > } >> > @@ -2608,17 +2608,17 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> > * values from table for which TX1 and TX2 enabled. >> > */ >> > for (ln = 0; ln < 2; ln++) { >> > - val = I915_READ(MG_CLKHUB(port, ln)); >> > + val = I915_READ(MG_CLKHUB(ln, port)); >> > if (link_clock < 300000) >> > val |= CFG_LOW_RATE_LKREN_EN; >> > else >> > val &= ~CFG_LOW_RATE_LKREN_EN; >> > - I915_WRITE(MG_CLKHUB(port, ln), val); >> > + I915_WRITE(MG_CLKHUB(ln, port), val); >> > } >> > >> > /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */ >> > for (ln = 0; ln < 2; ln++) { >> > - val = I915_READ(MG_TX1_DCC(port, ln)); >> > + val = I915_READ(MG_TX1_DCC(ln, port)); >> > val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; >> > if (link_clock <= 500000) { >> > val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; >> > @@ -2626,9 +2626,9 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> > val |= CFG_AMI_CK_DIV_OVERRIDE_EN | >> > CFG_AMI_CK_DIV_OVERRIDE_VAL(1); >> > } >> > - I915_WRITE(MG_TX1_DCC(port, ln), val); >> > + I915_WRITE(MG_TX1_DCC(ln, port), val); >> > >> > - val = I915_READ(MG_TX2_DCC(port, ln)); >> > + val = I915_READ(MG_TX2_DCC(ln, port)); >> > val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK; >> > if (link_clock <= 500000) { >> > val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN; >> > @@ -2636,18 +2636,18 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder, >> > val |= CFG_AMI_CK_DIV_OVERRIDE_EN | >> > CFG_AMI_CK_DIV_OVERRIDE_VAL(1); >> > } >> > - I915_WRITE(MG_TX2_DCC(port, ln), val); >> > + I915_WRITE(MG_TX2_DCC(ln, port), val); >> > } >> > >> > /* Program MG_TX_PISO_READLOAD with values from vswing table */ >> > for (ln = 0; ln < 2; ln++) { >> > - val = I915_READ(MG_TX1_PISO_READLOAD(port, ln)); >> > + val = I915_READ(MG_TX1_PISO_READLOAD(ln, port)); >> > val |= CRI_CALCINIT; >> > - I915_WRITE(MG_TX1_PISO_READLOAD(port, ln), val); >> > + I915_WRITE(MG_TX1_PISO_READLOAD(ln, port), val); >> > >> > - val = I915_READ(MG_TX2_PISO_READLOAD(port, ln)); >> > + val = I915_READ(MG_TX2_PISO_READLOAD(ln, port)); >> > val |= CRI_CALCINIT; >> > - I915_WRITE(MG_TX2_PISO_READLOAD(port, ln), val); >> > + I915_WRITE(MG_TX2_PISO_READLOAD(ln, port), val); >> > } >> > } >> > >> > -- >> > 2.17.1 >> > >> > _______________________________________________ >> > Intel-gfx mailing list >> > Intel-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx@lists.freedesktop.org >> https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Make macro definitions consistent in intel_reg.h 2019-01-28 22:00 [PATCH 0/2] Make macro definitions consistent in intel_reg.h Aditya Swarup 2019-01-28 22:00 ` [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL Aditya Swarup 2019-01-28 22:00 ` [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent Aditya Swarup @ 2019-01-28 23:00 ` Patchwork 2019-01-28 23:21 ` ✓ Fi.CI.BAT: success " Patchwork 2019-01-29 7:24 ` ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-01-28 23:00 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx == Series Details == Series: Make macro definitions consistent in intel_reg.h URL : https://patchwork.freedesktop.org/series/55875/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1eaa92c3b871 drm/i915: Make macro definitions consistent for ICL and CNL 504ef6aa90ba drm/i915: Make MG phy macros semantically consistent -:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'ln0p1' - possible side-effects? #23: FILE: drivers/gpu/drm/i915/i915_reg.h:1900: +#define MG_PHY_PORT_LN(ln, port, ln0p1, ln0p2, ln1p1) \ _MMIO(_PORT((port) - PORT_C, ln0p1, ln0p2) + (ln) * ((ln1p1) - (ln0p1))) total: 0 errors, 0 warnings, 1 checks, 243 lines checked _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for Make macro definitions consistent in intel_reg.h 2019-01-28 22:00 [PATCH 0/2] Make macro definitions consistent in intel_reg.h Aditya Swarup ` (2 preceding siblings ...) 2019-01-28 23:00 ` ✗ Fi.CI.CHECKPATCH: warning for Make macro definitions consistent in intel_reg.h Patchwork @ 2019-01-28 23:21 ` Patchwork 2019-01-29 7:24 ` ✓ Fi.CI.IGT: " Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-01-28 23:21 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx == Series Details == Series: Make macro definitions consistent in intel_reg.h URL : https://patchwork.freedesktop.org/series/55875/ State : success == Summary == CI Bug Log - changes from CI_DRM_5498 -> Patchwork_12064 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/55875/revisions/1/mbox/ Known issues ------------ Here are the changes found in Patchwork_12064 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_busy@basic-flip-b: - fi-gdg-551: PASS -> FAIL [fdo#103182] * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a: - fi-byt-clapper: PASS -> FAIL [fdo#103191] / [fdo#107362] +2 #### Possible fixes #### * igt@kms_busy@basic-flip-a: - fi-gdg-551: FAIL [fdo#103182] -> PASS * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: FAIL [fdo#109485] -> PASS * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: - fi-byt-clapper: FAIL [fdo#103191] / [fdo#107362] -> PASS * igt@pm_rpm@basic-pci-d3-state: - fi-byt-j1900: {SKIP} [fdo#109271] -> PASS * igt@pm_rpm@basic-rte: - fi-byt-j1900: FAIL [fdo#108800] -> PASS * igt@pm_rpm@module-reload: - fi-skl-6770hq: FAIL [fdo#108511] -> PASS [fdo#103182]: https://bugs.freedesktop.org/show_bug.cgi?id=103182 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#107362]: https://bugs.freedesktop.org/show_bug.cgi?id=107362 [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511 [fdo#108800]: https://bugs.freedesktop.org/show_bug.cgi?id=108800 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485 Participating hosts (44 -> 40) ------------------------------ Missing (4): fi-kbl-soraka fi-ilk-m540 fi-bsw-cyan fi-skl-6700hq Build changes ------------- * Linux: CI_DRM_5498 -> Patchwork_12064 CI_DRM_5498: bebd74b74f0c62ff61036fc2d349fc470502b565 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4796: d1bd9c6ad6f3482bbccf4aa6417dd449e9efbe39 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12064: 504ef6aa90bab8188ef6e9e09f7062cefc1bf2f6 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 504ef6aa90ba drm/i915: Make MG phy macros semantically consistent 1eaa92c3b871 drm/i915: Make macro definitions consistent for ICL and CNL == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12064/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.IGT: success for Make macro definitions consistent in intel_reg.h 2019-01-28 22:00 [PATCH 0/2] Make macro definitions consistent in intel_reg.h Aditya Swarup ` (3 preceding siblings ...) 2019-01-28 23:21 ` ✓ Fi.CI.BAT: success " Patchwork @ 2019-01-29 7:24 ` Patchwork 4 siblings, 0 replies; 10+ messages in thread From: Patchwork @ 2019-01-29 7:24 UTC (permalink / raw) To: Aditya Swarup; +Cc: intel-gfx == Series Details == Series: Make macro definitions consistent in intel_reg.h URL : https://patchwork.freedesktop.org/series/55875/ State : success == Summary == CI Bug Log - changes from CI_DRM_5498_full -> Patchwork_12064_full ==================================================== Summary ------- **WARNING** Minor unknown changes coming with Patchwork_12064_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_12064_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_12064_full: ### IGT changes ### #### Warnings #### * igt@kms_vblank@crtc-id: - shard-snb: {SKIP} [fdo#109271] -> FAIL Known issues ------------ Here are the changes found in Patchwork_12064_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-b: - shard-apl: PASS -> DMESG-WARN [fdo#107956] * igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: - shard-hsw: PASS -> FAIL [fdo#105767] * igt@kms_flip@modeset-vs-vblank-race: - shard-kbl: PASS -> FAIL [fdo#103060] * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133] * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max: - shard-kbl: NOTRUN -> FAIL [fdo#108145] * igt@kms_plane_multiple@atomic-pipe-a-tiling-x: - shard-apl: PASS -> FAIL [fdo#103166] +1 * igt@kms_plane_multiple@atomic-pipe-a-tiling-yf: - shard-glk: PASS -> FAIL [fdo#103166] #### Possible fixes #### * igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge: - shard-snb: {SKIP} [fdo#109271] / [fdo#109278] -> PASS * igt@kms_color@pipe-a-legacy-gamma: - shard-apl: FAIL [fdo#104782] / [fdo#108145] -> PASS +1 * igt@kms_cursor_crc@cursor-128x128-suspend: - shard-apl: FAIL [fdo#103191] / [fdo#103232] -> PASS * igt@kms_cursor_crc@cursor-64x64-onscreen: - shard-apl: FAIL [fdo#103232] -> PASS +2 * igt@kms_plane_multiple@atomic-pipe-b-tiling-y: - shard-glk: FAIL [fdo#103166] -> PASS - shard-apl: FAIL [fdo#103166] -> PASS +2 #### Warnings #### * igt@i915_suspend@shrink: - shard-kbl: INCOMPLETE [fdo#103665] / [fdo#106886] -> DMESG-WARN [fdo#109244] {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060 [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166 [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191 [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232 [fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782 [fdo#105767]: https://bugs.freedesktop.org/show_bug.cgi?id=105767 [fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886 [fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278 [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133 Participating hosts (6 -> 5) ------------------------------ Missing (1): shard-skl Build changes ------------- * Linux: CI_DRM_5498 -> Patchwork_12064 CI_DRM_5498: bebd74b74f0c62ff61036fc2d349fc470502b565 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4796: d1bd9c6ad6f3482bbccf4aa6417dd449e9efbe39 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_12064: 504ef6aa90bab8188ef6e9e09f7062cefc1bf2f6 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12064/ _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-02-14 13:38 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-01-28 22:00 [PATCH 0/2] Make macro definitions consistent in intel_reg.h Aditya Swarup 2019-01-28 22:00 ` [PATCH 1/2] drm/i915: Make macro definitions consistent for ICL and CNL Aditya Swarup 2019-02-12 23:58 ` Manasi Navare 2019-01-28 22:00 ` [PATCH 2/2] drm/i915: Make MG phy macros semantically consistent Aditya Swarup 2019-02-12 23:59 ` Manasi Navare 2019-02-14 7:47 ` Lucas De Marchi 2019-02-14 13:39 ` Jani Nikula 2019-01-28 23:00 ` ✗ Fi.CI.CHECKPATCH: warning for Make macro definitions consistent in intel_reg.h Patchwork 2019-01-28 23:21 ` ✓ Fi.CI.BAT: success " Patchwork 2019-01-29 7:24 ` ✓ Fi.CI.IGT: " Patchwork
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