Re: [PATCH 2/9] drm/i915: Fix PLL 8x/3 divider for MIPI video mode

[Jani Nikula <jani.nikula@intel.com>]

On Wed, 08 Feb 2017, Vidya Srinivas <vidya.srinivas@intel.com> wrote:
> From: Uma Shankar <uma.shankar@intel.com>
>
> MIPI Video Mode for high res panels (requiring dual link), need a
> 8X/3 divider to be programmed as 0x2. Modifying the same
> in this patch.
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>

Pushed the first two patches to drm-intel-next-queued, thanks for the
patches.

BR,
Jani.

> ---
>  drivers/gpu/drm/i915/intel_dsi_pll.c | 6 +-----
>  1 file changed, 1 insertion(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 61440e5..3a73086 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -416,11 +416,7 @@ static void bxt_dsi_program_clocks(struct drm_device *dev, enum port port,
>  	rx_div_lower = rx_div & RX_DIVIDER_BIT_1_2;
>  	rx_div_upper = (rx_div & RX_DIVIDER_BIT_3_4) >> 2;
>  
> -	/* As per bpsec program the 8/3X clock divider to the below value */
> -	if (dev_priv->vbt.dsi.config->is_cmd_mode)
> -		mipi_8by3_divider = 0x2;
> -	else
> -		mipi_8by3_divider = 0x3;
> +	mipi_8by3_divider = 0x2;
>  
>  	tmp |= BXT_MIPI_8X_BY3_DIVIDER(port, mipi_8by3_divider);
>  	tmp |= BXT_MIPI_TX_ESCLK_DIVIDER(port, tx_div);

-- 
Jani Nikula, Intel Open Source Technology Center
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