From: Jani Nikula <jani.nikula@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, libin.yang@intel.com,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>,
stable@vger.kernel.org, Libin Yang <libin.yang@linux.intel.com>
Subject: Re: [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms
Date: Tue, 01 Nov 2016 21:35:20 +0200 [thread overview]
Message-ID: <874m3rj8nb.fsf@intel.com> (raw)
In-Reply-To: <1478026080-2925-2-git-send-email-dhinakaran.pandiyan@intel.com>
On Tue, 01 Nov 2016, Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> wrote:
> According to BSpec, cdclk for BDW has to be not less than 432 MHz with DP
> audio enabled, port width x4, and link rate HBR2 (5.4 GHz). With cdclk less
> than 432 MHz, enabling audio leads to pipe FIFO underruns and displays
> cycling on/off.
>
> Let's apply this work around to GEN9 platforms too, as it fixes the same
> issue.
I'm too tired to read bspec now, but is gen9 really the answer, or just
Skylake?
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97907
> Cc: stable@vger.kernel.org
> Cc: Libin Yang <libin.yang@linux.intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 37483ee..c0ae147 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -10264,8 +10264,10 @@ static void bxt_modeset_commit_cdclk(struct drm_atomic_state *old_state)
> static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
> int pixel_rate)
> {
> + struct drm_device *dev = crtc_state->base.crtc->dev;
Nitpick, I guess I'd make that
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
but no big deal.
> +
> /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
> - if (crtc_state->ips_enabled)
> + if (IS_BROADWELL(to_i915(dev)) && crtc_state->ips_enabled)
> pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
>
> /* BSpec says "Do not use DisplayPort with CDCLK less than
> @@ -10307,7 +10309,7 @@ static int ilk_max_pixel_rate(struct drm_atomic_state *state)
>
> pixel_rate = ilk_pipe_pixel_rate(crtc_state);
>
> - if (IS_BROADWELL(dev_priv))
> + if (IS_BROADWELL(dev_priv) || IS_GEN9(dev_priv))
> pixel_rate = bdw_adjust_min_pipe_pixel_rate(crtc_state,
> pixel_rate);
--
Jani Nikula, Intel Open Source Technology Center
next prev parent reply other threads:[~2016-11-01 19:35 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 18:47 [PATCH v4 1/2] drm/i915/dp: BDW cdclk fix for DP audio Dhinakaran Pandiyan
2016-11-01 18:48 ` [PATCH v4 2/2] drm/i915/dp: Extend BDW DP audio workaround to GEN9 platforms Dhinakaran Pandiyan
2016-11-01 19:35 ` Jani Nikula [this message]
2016-11-01 19:42 ` Pandiyan, Dhinakaran
2016-11-01 19:50 ` Jani Nikula
2016-11-02 20:15 ` [Intel-gfx] " Pandiyan, Dhinakaran
2016-11-02 20:13 ` [PATCH v5 " Dhinakaran Pandiyan
2016-11-01 19:16 ` ✗ Fi.CI.BAT: warning for series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio Patchwork
2016-11-01 19:28 ` [PATCH v4 1/2] " Jani Nikula
2016-11-02 20:46 ` ✗ Fi.CI.BAT: warning for series starting with [v4,1/2] drm/i915/dp: BDW cdclk fix for DP audio (rev2) Patchwork
2016-11-04 15:44 ` Jani Nikula
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