From mboxrd@z Thu Jan 1 00:00:00 1970 From: Francisco Jerez Subject: Re: [PATCH] drm/i915/skl: Default to noncoherent access up to F0 Date: Fri, 18 Dec 2015 16:40:42 +0200 Message-ID: <874mff3jmd.fsf@riseup.net> References: <1450448093-22906-1-git-send-email-mika.kuoppala@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0640232775==" Return-path: Received: from mx1.riseup.net (mx1.riseup.net [198.252.153.129]) by gabe.freedesktop.org (Postfix) with ESMTPS id E85176E1FC for ; Fri, 18 Dec 2015 06:41:13 -0800 (PST) In-Reply-To: <1450448093-22906-1-git-send-email-mika.kuoppala@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Mika Kuoppala , intel-gfx@lists.freedesktop.org Cc: Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org --===============0640232775== Content-Type: multipart/signed; boundary="==-=-="; micalg=pgp-sha256; protocol="application/pgp-signature" --==-=-= Content-Type: multipart/mixed; boundary="=-=-=" --=-=-= Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Mika Kuoppala writes: > The workarounds for disabling hdc invalidation and also forcing > context to be non coherent, are advised to be used up until rev D0. > > However as it was found that rev F0, without the > WaForceEnableNonCoherent might system hang if the mesa > tried to use coherent mode. > > As these two workarounds are about non coherent access, are > grouped in scope and they point the same HSD, increase the > scope of both to set default behaviour to non coherent access. > > References: HSD: gen9lp/2131413 > References: http://lists.freedesktop.org/archives/mesa-dev/2015-November/= 101515.html > Cc: Ben Widawsky > Cc: Francisco Jerez > Signed-off-by: Mika Kuoppala > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index eefce9a3e9c8..339701d7a9a5 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1018,10 +1018,6 @@ static int skl_init_workarounds(struct intel_engin= e_cs *ring) > return ret; >=20=20 > if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { > - /* WaDisableHDCInvalidation:skl */ > - I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > - BDW_DISABLE_HDC_INVALIDATION); > - > /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ > I915_WRITE(FF_SLICE_CS_CHICKEN2, > _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE)); > @@ -1046,7 +1042,7 @@ static int skl_init_workarounds(struct intel_engine= _cs *ring) > WA_SET_BIT_MASKED(HIZ_CHICKEN, > BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE); >=20=20 > - if (IS_SKL_REVID(dev, 0, SKL_REVID_D0)) { > + if (IS_SKL_REVID(dev, 0, SKL_REVID_F0)) { > /* > *Use Force Non-Coherent whenever executing a 3D context. This > * is a workaround for a possible hang in the unlikely event > @@ -1055,6 +1051,10 @@ static int skl_init_workarounds(struct intel_engin= e_cs *ring) > /* WaForceEnableNonCoherent:skl */ > WA_SET_BIT_MASKED(HDC_CHICKEN0, > HDC_FORCE_NON_COHERENT); > + > + /* WaDisableHDCInvalidation:skl */ > + I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > + BDW_DISABLE_HDC_INVALIDATION); Looks good to me, Reviewed-by: Francisco Jerez > } >=20=20 > /* WaBarrierPerformanceFixDisable:skl */ > --=20 > 2.5.0 --=-=-=-- --==-=-= Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iF4EAREIAAYFAlZ0GuoACgkQg5k4nX1Sv1vDowD+OKu84P/kloE/tfWDvLHvz08E 3778YfDdUIWke2eLBsMBAJjzkByEQDb3fEXuaBjQ687O6xtc/lahrhpNpgaydgYD =8yEr -----END PGP SIGNATURE----- --==-=-=-- --===============0640232775== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHA6Ly9saXN0 cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5mby9pbnRlbC1nZngK --===============0640232775==--