From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jani Nikula Subject: Re: [PATCH 50/62] drm/i915/bdw: Support eDP PSR Date: Mon, 04 Nov 2013 12:34:21 +0200 Message-ID: <874n7scv6a.fsf@intel.com> References: <1383451680-11173-1-git-send-email-benjamin.widawsky@intel.com> <1383451680-11173-51-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 812A2FA1F1 for ; Mon, 4 Nov 2013 02:32:30 -0800 (PST) In-Reply-To: <1383451680-11173-51-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org To: Intel GFX Cc: Ben Widawsky , Art Runyan , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Sun, 03 Nov 2013, Ben Widawsky wrote: > Broadwell PSR support is a superset of Haswell. With this simple > register base calculation, everything that worked on HSW for eDP PSR > should work on BDW. Per bspec, EDP_PSR_CTL register EDP_PSR_MIN_LINK_ENTRY_TIME_* bits are reserved/MBZ on BDW, but intel_edp_psr_enable_source() sets them. With that fixed, Reviewed-by: Jani Nikula > Note that Broadwell provides additional PSR support. This is not > addressed at this time. > > v2: Make the HAS_PSR include BDW > > v3: Use the correct offset (I had incorrectly used one from my faulty > brain) (Art!) > > v4: It helps if you git add > > CC: Art Runyan > Reviewed-by: Art Runyan > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index f222eb4..dc79a0f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1808,7 +1808,7 @@ struct drm_i915_file_private { > #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) > #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_GEN8(dev)) > #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) > -#define HAS_PSR(dev) (IS_HASWELL(dev)) > +#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) > > #define INTEL_PCH_DEVICE_ID_MASK 0xff00 > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 65f9631..f97836e 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1956,8 +1956,8 @@ > #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) > #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) > > -/* HSW eDP PSR registers */ > -#define EDP_PSR_BASE(dev) 0x64800 > +/* HSW+ eDP PSR registers */ > +#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) > #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) > #define EDP_PSR_ENABLE (1<<31) > #define EDP_PSR_LINK_DISABLE (0<<27) > -- > 1.8.4.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Technology Center