From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D2E4BC433FE for ; Thu, 29 Sep 2022 11:58:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E068010E5E0; Thu, 29 Sep 2022 11:58:48 +0000 (UTC) Received: from mga06.intel.com (mga06b.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2681C10E5E0 for ; Thu, 29 Sep 2022 11:58:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1664452726; x=1695988726; h=from:to:subject:in-reply-to:references:date:message-id: mime-version:content-transfer-encoding; bh=KXY8H0WxmwXQ1hWY+rKmzLdLhExv7L00ZXc9Ef1WIPo=; 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Intel-gfx] [PATCH 05/10] drm/i915: Change glk_load_degamma_lut() calling convention X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 29 Sep 2022, Ville Syrjala wrote: > From: Ville Syrj=C3=A4l=C3=A4 > > Make glk_load_degamma_lut() more like most everyone else and > pass in the LUT explicitly. > > Signed-off-by: Ville Syrj=C3=A4l=C3=A4 Reviewed-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_color.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm= /i915/display/intel_color.c > index 96687ec30b19..0c73b2ba1283 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -826,13 +826,14 @@ static int glk_degamma_lut_size(struct drm_i915_pri= vate *i915) > return 35; > } >=20=20 > -static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_sta= te) > +static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_sta= te, > + const struct drm_property_blob *blob) > { > struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *dev_priv =3D to_i915(crtc->base.dev); > + const struct drm_color_lut *lut =3D blob->data; > + int i, lut_size =3D drm_color_lut_size(blob); > enum pipe pipe =3D crtc->pipe; > - int i, lut_size =3D INTEL_INFO(dev_priv)->display.color.degamma_lut_siz= e; > - const struct drm_color_lut *lut =3D crtc_state->hw.degamma_lut->data; >=20=20 > /* > * When setting the auto-increment bit, the hardware seems to > @@ -899,6 +900,7 @@ static void glk_load_degamma_lut_linear(const struct = intel_crtc_state *crtc_stat >=20=20 > static void glk_load_luts(const struct intel_crtc_state *crtc_state) > { > + const struct drm_property_blob *degamma_lut =3D crtc_state->hw.degamma_= lut; > const struct drm_property_blob *gamma_lut =3D crtc_state->hw.gamma_lut; > struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); >=20=20 > @@ -910,8 +912,8 @@ static void glk_load_luts(const struct intel_crtc_sta= te *crtc_state) > * the degama LUT so that we don't have to reload > * it every time the pipe CSC is being enabled. > */ > - if (crtc_state->hw.degamma_lut) > - glk_load_degamma_lut(crtc_state); > + if (degamma_lut) > + glk_load_degamma_lut(crtc_state, degamma_lut); > else > glk_load_degamma_lut_linear(crtc_state); >=20=20 > @@ -1043,11 +1045,12 @@ icl_program_gamma_multi_segment(const struct inte= l_crtc_state *crtc_state) >=20=20 > static void icl_load_luts(const struct intel_crtc_state *crtc_state) > { > + const struct drm_property_blob *degamma_lut =3D crtc_state->hw.degamma_= lut; > const struct drm_property_blob *gamma_lut =3D crtc_state->hw.gamma_lut; > struct intel_crtc *crtc =3D to_intel_crtc(crtc_state->uapi.crtc); >=20=20 > - if (crtc_state->hw.degamma_lut) > - glk_load_degamma_lut(crtc_state); > + if (degamma_lut) > + glk_load_degamma_lut(crtc_state, degamma_lut); >=20=20 > switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) { > case GAMMA_MODE_MODE_8BIT: --=20 Jani Nikula, Intel Open Source Graphics Center