From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD2DAC54EE9 for ; Tue, 13 Sep 2022 15:40:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A5BB10E401; Tue, 13 Sep 2022 15:40:32 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 50F9910E401 for ; Tue, 13 Sep 2022 15:40:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663083628; x=1694619628; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=Wflpjg1doRBwdwx5uT2RWA64tZ1HmzfoV4/H5ZAmSrI=; b=SAUQGnq/AjSqCCyDYb/N4L0XRI+b4l2NuDpfh0KIMDDxV3QEWaB0osq/ oDQhddMf3kX51KzKWQYEv2NXHnFFV4s3DXATalHDIc4tQ0bum2fO8r+Hm a/nvup1wl84rqLERPf7Mi5PMcTpptgkhkjDoO98so+62kID+LGmxEBynK 8JK7t4BL0BdxKM43rbpxEux4REdyzdVcuzG3Fca3C/oO6waDVAZGZYWPg OekScdt8/1XNuIk33jTIQ3EBSWc/tfzEf4qoAhxt9R6TM0S1BGM+25WpY 0K21ES8mMjKtpFAhFa2qSiXkA5cUcjuFF1JP0lJBqIHbY9WBTy53Dwqxu Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10469"; a="278563095" X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="278563095" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 08:40:27 -0700 X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="861594665" Received: from epryes-mobl3.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.210.47]) by fmsmga006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Sep 2022 08:40:27 -0700 Date: Tue, 13 Sep 2022 08:40:22 -0700 Message-ID: <875yhr5lll.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Umesh Nerlige Ramappa In-Reply-To: <20220823204155.8178-3-umesh.nerlige.ramappa@intel.com> References: <20220823204155.8178-1-umesh.nerlige.ramappa@intel.com> <20220823204155.8178-3-umesh.nerlige.ramappa@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 02/19] drm/i915/perf: Add OA formats for DG2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Tue, 23 Aug 2022 13:41:38 -0700, Umesh Nerlige Ramappa wrote: > > Add new OA formats for DG2. Should we change the patch title and commit message a bit to 'Add OAR and OAG formats for DG2'? > Some of the newer OA formats are not > multples of 64 bytes and are not powers of 2. For those formats, adjust > hw_tail accordingly when checking for new reports. > > Signed-off-by: Umesh Nerlige Ramappa > --- > drivers/gpu/drm/i915/i915_perf.c | 63 ++++++++++++++++++++------------ > include/uapi/drm/i915_drm.h | 6 +++ > 2 files changed, 46 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 735244a3aedd..c8331b549d31 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -306,7 +306,8 @@ static u32 i915_oa_max_sample_rate = 100000; > > /* XXX: beware if future OA HW adds new report formats that the current > * code assumes all reports have a power-of-two size and ~(size - 1) can > - * be used as a mask to align the OA tail pointer. > + * be used as a mask to align the OA tail pointer. In some of the > + * formats, R is used to denote reserved field. > */ > static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = { > [I915_OA_FORMAT_A13] = { 0, 64 }, > @@ -320,6 +321,10 @@ static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = { > [I915_OA_FORMAT_A12] = { 0, 64 }, > [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 }, > [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 }, > + [I915_OAR_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 }, > + [I915_OA_FORMAT_A24u40_A14u32_B8_C8] = { 5, 256 }, > + [I915_OAR_FORMAT_A36u64_B8_C8] = { 1, 384 }, > + [I915_OA_FORMAT_A38u64_R2u64_B8_C8] = { 1, 448 }, Isn't the size for this last one 416 (or 400)? Bspec: 52198. Unless the size has to be a multiple of 64? Looks like Lionel's R-b is not showing up on Patchwork, might need to be manually added. For now this is: Acked-by: Ashutosh Dixit