From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E9771C54EE9 for ; Thu, 8 Sep 2022 15:52:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DE48110EA00; Thu, 8 Sep 2022 15:52:23 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4848B10EA00 for ; Thu, 8 Sep 2022 15:52:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662652340; x=1694188340; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=g52c5UfvnFqGT+1is8DhBkMlE284FyX2rElG8noqDj8=; b=XEpAzi7kgMlcO93YpLfXlf93XXHIE1IxuciZ5ZlGYAWGRVZW9hSxSqut Hy8RUNM9mSkr33boZJ/YZi9tQxbixBwcLdHcXhHJUItlVsqUpGVPBEE+I IDkMjwM/SnPQNPN/oaAHOcrGWdludW89r5PHF2XITix2M6dUPxN/cLeNz 76XEUeubnLH50wGwlQIMNBpcIeG+5wGhhDygNij5R+AxeyecNQtuoeGjE lFOpWCdXO3NMxBtF9ndRHOTabCdc+zjQcoaNJvBX7xMU4znVP3RzraBWJ 1kkqw7qVysxGN0uAMRGN2PTeaO0+/5xws8Ow5AVMYO4wrt8Kh1n10iQqG g==; X-IronPort-AV: E=McAfee;i="6500,9779,10464"; a="277612991" X-IronPort-AV: E=Sophos;i="5.93,300,1654585200"; d="scan'208";a="277612991" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2022 08:52:19 -0700 X-IronPort-AV: E=Sophos;i="5.93,300,1654585200"; d="scan'208";a="565994921" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.161.89]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Sep 2022 08:52:18 -0700 Date: Thu, 08 Sep 2022 08:49:42 -0700 Message-ID: <875yhxyig9.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Sundaresan, Sujaritha" In-Reply-To: <4a2b75d2-4605-07a1-4b06-425aa09b4738@intel.com> References: <4a2b75d2-4605-07a1-4b06-425aa09b4738@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-gfx] [PATCH 5/8] drm/i915/gt: Fix perf limit reasons bit positions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-gfx@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" On Thu, 08 Sep 2022 05:37:08 -0700, Sundaresan, Sujaritha wrote: > > On 9/8/2022 4:12 PM, Andi Shyti wrote: > > Hi, > > > > On Wed, Sep 07, 2022 at 10:21:53PM -0700, Ashutosh Dixit wrote: > >> Perf limit reasons bit positions were off by one. > >> > >> Fixes: fa68bff7cf27 ("drm/i915/gt: Add sysfs throttle frequency interfaces") > >> Cc: stable@vger.kernel.org # v5.18+ > >> Cc: Sujaritha Sundaresan > >> Cc: Andi Shyti > >> Signed-off-by: Ashutosh Dixit > > Thanks Ashutosh! > > > >> --- > >> drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++-------- > >> 1 file changed, 8 insertions(+), 8 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > >> index c413eec3373f..24009786f88b 100644 > >> --- a/drivers/gpu/drm/i915/i915_reg.h > >> +++ b/drivers/gpu/drm/i915/i915_reg.h > >> @@ -1794,14 +1794,14 @@ > >> #define GT0_PERF_LIMIT_REASONS _MMIO(0x1381a8) > >> #define GT0_PERF_LIMIT_REASONS_MASK 0xde3 > >> -#define PROCHOT_MASK REG_BIT(1) > >> -#define THERMAL_LIMIT_MASK REG_BIT(2) > >> -#define RATL_MASK REG_BIT(6) > >> -#define VR_THERMALERT_MASK REG_BIT(7) > >> -#define VR_TDC_MASK REG_BIT(8) > >> -#define POWER_LIMIT_4_MASK REG_BIT(9) > >> -#define POWER_LIMIT_1_MASK REG_BIT(11) > >> -#define POWER_LIMIT_2_MASK REG_BIT(12) > >> +#define PROCHOT_MASK REG_BIT(0) > >> +#define THERMAL_LIMIT_MASK REG_BIT(1) > >> +#define RATL_MASK REG_BIT(5) > >> +#define VR_THERMALERT_MASK REG_BIT(6) > >> +#define VR_TDC_MASK REG_BIT(7) > >> +#define POWER_LIMIT_4_MASK REG_BIT(8) > >> +#define POWER_LIMIT_1_MASK REG_BIT(10) > >> +#define POWER_LIMIT_2_MASK REG_BIT(11) > > Sujaritha, could you please check and r-b this one? > > > > Thanks, > > Andi > > Looks good. I've checked the reg bits. > > Reviewed-by : Sujaritha Sundaresan ^ I will fix it so no need to resend but just FYI Patchwork doesn't like the extra space above so doesn't register the R-b...