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From: Mika Kuoppala <mika.kuoppala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH] drm/i915/cnl:	WaForceContextSaveRestoreNonCoherent
Date: Wed, 27 Sep 2017 13:37:42 +0300	[thread overview]
Message-ID: <8760c4zatl.fsf@gaia.fi.intel.com> (raw)
In-Reply-To: <150650399988.4369.15946530619569421703@mail.alporthouse.com>

Chris Wilson <chris@chris-wilson.co.uk> writes:

> Quoting Rodrigo Vivi (2017-08-23 00:27:15)
>> To avoid a potential hang condition with TLB invalidation
>> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>> 
>> Same workaround was in place for previous platforms,
>> but the change for CNL is more on the register offset.
>> But also BSpec doesn't mention the bit 15 as set on gen9
>> platforms and mark bit as reserved on CNL.
>> 
>> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> Cc: Oscar Mateo <oscar.mateo@intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>>  2 files changed, 5 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d4ecb1905ad8..f31fab2651fb 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7024,6 +7024,7 @@ enum {
>>  
>>  /* GEN8 chicken */
>>  #define HDC_CHICKEN0                           _MMIO(0x7300)
>> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
>>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
>>  #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
>>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
>> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
>> index d23f18874309..26c35ce5f240 100644
>> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
>> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>>         struct drm_i915_private *dev_priv = engine->i915;
>>         int ret;
>>  
>> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
>> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
>> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
>
> This register is not sticky (i.e. does not retain its value even with a
> powercontext loaded). Does it even exist?
> -Chris

That is a good question. The documentation indicates it does
and evidence indicates that it doesn't.

I will check when I get cnl unless someone beats me to it.

-Mika

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  reply	other threads:[~2017-09-27 10:39 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-08-22 23:27 [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Rodrigo Vivi
2017-08-22 23:43 ` ✓ Fi.CI.BAT: success for " Patchwork
2017-08-23 20:00 ` [PATCH] " Oscar Mateo
2017-08-23 20:35   ` Rodrigo Vivi
2017-08-23 21:48     ` Rodrigo Vivi
2017-08-23 21:30 ` ✓ Fi.CI.BAT: success for drm/i915/cnl: WaForceContextSaveRestoreNonCoherent (rev2) Patchwork
2017-09-27  9:19 ` [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent Chris Wilson
2017-09-27 10:37   ` Mika Kuoppala [this message]
2017-09-27 17:37     ` Oscar Mateo
2017-09-27 17:42       ` Chris Wilson
2017-09-28  9:46       ` Chris Wilson
2017-09-28 20:56         ` Oscar Mateo
2017-09-28 21:38           ` Oscar Mateo

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