Re: [PATCH 2/2] drm/i915/gen9: fix watermarks when using the pipe scaler

[Jani Nikula <jani.nikula@linux.intel.com>]

On Fri, 07 Oct 2016, "Zanoni, Paulo R" <paulo.r.zanoni@intel.com> wrote:
> Em Sex, 2016-10-07 às 17:13 -0300, Paulo Zanoni escreveu:
>> Luckily, the necessary adjustments for when we're using the scaler
>> are
>> exactly the same as the ones needed on ILK+, so just reuse the
>> function we already have.
>
> Now that I sent it, I realized that I should just have inverted the
> patch order so patch 1 could be Cc:stable to ease backporting...

Seems to me patch 1/2 is also useful for backporting if patch 2/2 gets
backported. cc: stable to both, with the dependency added to patch 2/2
when we have the commit id for 1/2 (done while applying).

Documentation/stable_kernel_rules.txt:

"""
Additionally, some patches submitted via Option 1 may have additional patch
prerequisites which can be cherry-picked. This can be specified in the following
format in the sign-off area:

     Cc: <stable@vger.kernel.org> # 3.3.x: a1f84a3: sched: Check for idle
     Cc: <stable@vger.kernel.org> # 3.3.x: 1b9508f: sched: Rate-limit newidle
     Cc: <stable@vger.kernel.org> # 3.3.x: fd21073: sched: Fix affinity logic
     Cc: <stable@vger.kernel.org> # 3.3.x
    Signed-off-by: Ingo Molnar <mingo@elte.hu>

   The tag sequence has the meaning of:
     git cherry-pick a1f84a3
     git cherry-pick 1b9508f
     git cherry-pick fd21073
     git cherry-pick <this commit>
"""

BR,
Jani.

>
>> 
>> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_pm.c | 10 ++--------
>>  1 file changed, 2 insertions(+), 8 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 3a6df2f..62d730d 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -3470,12 +3470,6 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
>> *cstate,
>>  	return 0;
>>  }
>>  
>> -static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state
>> *config)
>> -{
>> -	/* TODO: Take into account the scalers once we support them
>> */
>> -	return config->base.adjusted_mode.crtc_clock;
>> -}
>> -
>>  /*
>>   * The max latency should be 257 (max the punit can code is 255 and
>> we add 2us
>>   * for the read latency) and cpp should always be <= 8, so that
>> @@ -3526,7 +3520,7 @@ static uint32_t
>> skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cst
>>  	 * Adjusted plane pixel rate is just the pipe's adjusted
>> pixel rate
>>  	 * with additional adjustments for plane-specific scaling.
>>  	 */
>> -	adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
>> +	adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
>>  	downscale_amount = skl_plane_downscale_amount(pstate);
>>  
>>  	pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
>> @@ -3744,7 +3738,7 @@ skl_compute_linetime_wm(struct intel_crtc_state
>> *cstate)
>>  	if (!cstate->base.active)
>>  		return 0;
>>  
>> -	pixel_rate = skl_pipe_pixel_rate(cstate);
>> +	pixel_rate = ilk_pipe_pixel_rate(cstate);
>>  
>>  	if (WARN_ON(pixel_rate == 0))
>>  		return 0;
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-- 
Jani Nikula, Intel Open Source Technology Center
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