* drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ?
@ 2016-05-30 10:32 David Binderman
2016-05-30 12:54 ` [PATCH] drm/i915: fix BSM_MASK definition Jani Nikula
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: David Binderman @ 2016-05-30 10:32 UTC (permalink / raw)
To: daniel.vetter, jani.nikula, airlied, intel-gfx, dri-devel, dcb314
Hello there,
drivers/gpu/drm/i915/i915_reg.h:90:28: warning: result of ‘65535 <<
20’ requires 37 bits to represent, but ‘int’ only has 32 bits
[-Wshift-overflow=]
Source code is
#define BSM_MASK (0xFFFF << 20)
Maybe better code
#define BSM_MASK (((unsigned long) 0xFFFF) << 20)
Regards
David Binderman
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^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH] drm/i915: fix BSM_MASK definition
2016-05-30 10:32 drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? David Binderman
@ 2016-05-30 12:54 ` Jani Nikula
2016-05-30 14:15 ` drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? Chris Wilson
2016-05-31 9:56 ` ✗ Ro.CI.BAT: failure for drm/i915: fix BSM_MASK definition Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-05-30 12:54 UTC (permalink / raw)
To: David Binderman, daniel.vetter, jani.nikula, airlied, intel-gfx,
dri-devel, dcb314
Cc: Jani Nikula
The PCI config space BSM (Base of Stolen Memory) register has bits
20..31 set. The BSM_MASK definition goes beyond 32 bits, fix it.
drivers/gpu/drm/i915/i915_reg.h:90:28: warning: result of ‘65535 << 20’
requires 37 bits to represent, but ‘int’ only has 32 bits
[-Wshift-overflow=]
References: http://mid.gmane.org/CAMzoambf23FJH3Lq-gKcrVEus-bqFLxA35n0YjKGhqWOAJdBqg@mail.gmail.com
Reported-by: David Binderman <linuxdev.baldrick@gmail.com>
Cc: David Binderman <linuxdev.baldrick@gmail.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Fixes: e10fa551ae37 ("drm/i915: Clean up PCI config register handling")
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b407411e31ba..769ac8f7ab61 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -87,7 +87,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define DEVEN_MCHBAR_EN (1 << 28)
#define BSM 0x5c
-#define BSM_MASK (0xFFFF << 20)
+#define BSM_MASK (0xFFF << 20)
#define HPLLCC 0xc0 /* 85x only */
#define GC_CLOCK_CONTROL_MASK (0x7 << 0)
--
2.1.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ?
2016-05-30 10:32 drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? David Binderman
2016-05-30 12:54 ` [PATCH] drm/i915: fix BSM_MASK definition Jani Nikula
@ 2016-05-30 14:15 ` Chris Wilson
2016-05-30 14:51 ` Jani Nikula
2016-05-31 9:56 ` ✗ Ro.CI.BAT: failure for drm/i915: fix BSM_MASK definition Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Chris Wilson @ 2016-05-30 14:15 UTC (permalink / raw)
To: David Binderman; +Cc: intel-gfx, dri-devel, dcb314, daniel.vetter
On Mon, May 30, 2016 at 11:32:59AM +0100, David Binderman wrote:
> Hello there,
>
> drivers/gpu/drm/i915/i915_reg.h:90:28: warning: result of ‘65535 <<
> 20’ requires 37 bits to represent, but ‘int’ only has 32 bits
> [-Wshift-overflow=]
>
> Source code is
>
> #define BSM_MASK (0xFFFF << 20)
>
> Maybe better code
>
> #define BSM_MASK (((unsigned long) 0xFFFF) << 20)
#define BSM_MASK (~0u << 20)
It should be a 32bit mask. The current (with the exception of undefined
behaviour of shifting into the signbit, fortunately gcc does what we
expect) code is functionally current as the mask will be truncated to
32bits.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ?
2016-05-30 14:15 ` drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? Chris Wilson
@ 2016-05-30 14:51 ` Jani Nikula
0 siblings, 0 replies; 5+ messages in thread
From: Jani Nikula @ 2016-05-30 14:51 UTC (permalink / raw)
To: Chris Wilson, David Binderman; +Cc: intel-gfx, dri-devel, dcb314, daniel.vetter
On Mon, 30 May 2016, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Mon, May 30, 2016 at 11:32:59AM +0100, David Binderman wrote:
>> Hello there,
>>
>> drivers/gpu/drm/i915/i915_reg.h:90:28: warning: result of ‘65535 <<
>> 20’ requires 37 bits to represent, but ‘int’ only has 32 bits
>> [-Wshift-overflow=]
>>
>> Source code is
>>
>> #define BSM_MASK (0xFFFF << 20)
>>
>> Maybe better code
>>
>> #define BSM_MASK (((unsigned long) 0xFFFF) << 20)
>
> #define BSM_MASK (~0u << 20)
>
> It should be a 32bit mask. The current (with the exception of undefined
> behaviour of shifting into the signbit, fortunately gcc does what we
> expect) code is functionally current as the mask will be truncated to
> 32bits.
In the patch I used BSM_MASK (0xFFF << 20). It does have the UB of
shifting into the sign bit, but then we have loads of e.g. (1 << 31) in
i915_reg.h which is no different.
The original code before e10fa551ae37b had ~((1<<20) - 1).
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
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^ permalink raw reply [flat|nested] 5+ messages in thread
* ✗ Ro.CI.BAT: failure for drm/i915: fix BSM_MASK definition
2016-05-30 10:32 drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? David Binderman
2016-05-30 12:54 ` [PATCH] drm/i915: fix BSM_MASK definition Jani Nikula
2016-05-30 14:15 ` drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? Chris Wilson
@ 2016-05-31 9:56 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2016-05-31 9:56 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: fix BSM_MASK definition
URL : https://patchwork.freedesktop.org/series/7982/
State : failure
== Summary ==
Series 7982v1 drm/i915: fix BSM_MASK definition
http://patchwork.freedesktop.org/api/1.0/series/7982/revisions/1/mbox
Test gem_close_race:
Subgroup basic-process:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Test gem_exec_basic:
Subgroup basic-render:
pass -> DMESG-WARN (ro-ivb2-i7-3770)
Subgroup readonly-render:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_exec_flush:
Subgroup basic-uc-ro-default:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup basic-wb-prw-default:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_exec_store:
Subgroup basic-blt:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Subgroup basic-default:
dmesg-warn -> PASS (ro-ivb2-i7-3770)
Test gem_mmap_gtt:
Subgroup basic-small-copy:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup basic-write-no-prefault:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_pwrite:
Subgroup basic:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test gem_storedw_loop:
Subgroup basic-bsd:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup basic-render:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_addfb_basic:
Subgroup addfb25-framebuffer-vs-set-tiling:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup addfb25-x-tiled:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup addfb25-y-tiled-small:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup bad-pitch-1024:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup bad-pitch-63:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup framebuffer-vs-set-tiling:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Subgroup too-high:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup too-wide:
dmesg-warn -> PASS (ro-skl-i7-6700hq)
Subgroup unused-offsets:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_force_connector_basic:
Subgroup force-edid:
pass -> DMESG-WARN (ro-ivb2-i7-3770)
Test kms_pipe_crc_basic:
Subgroup suspend-read-crc-pipe-b:
pass -> INCOMPLETE (fi-hsw-i7-4770k)
Test kms_setmode:
Subgroup basic-clone-single-crtc:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
Test kms_sink_crc_basic:
pass -> DMESG-WARN (ro-skl-i7-6700hq)
fi-bdw-i7-5557u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
fi-hsw-i7-4770k total:190 pass:172 dwarn:0 dfail:0 fail:0 skip:17
fi-hsw-i7-4770r total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
fi-skl-i7-6700k total:209 pass:184 dwarn:0 dfail:0 fail:0 skip:25
fi-snb-i7-2600 total:209 pass:170 dwarn:0 dfail:0 fail:0 skip:39
ro-bdw-i5-5250u total:102 pass:93 dwarn:0 dfail:0 fail:0 skip:8
ro-bsw-n3050 total:209 pass:168 dwarn:0 dfail:0 fail:2 skip:39
ro-byt-n2820 total:209 pass:169 dwarn:0 dfail:0 fail:3 skip:37
ro-hsw-i3-4010u total:209 pass:186 dwarn:0 dfail:0 fail:0 skip:23
ro-hsw-i7-4770r total:102 pass:82 dwarn:0 dfail:0 fail:0 skip:19
ro-ilk-i7-620lm total:1 pass:0 dwarn:0 dfail:0 fail:0 skip:0
ro-ilk1-i5-650 total:204 pass:146 dwarn:0 dfail:0 fail:1 skip:57
ro-ivb-i7-3770 total:102 pass:75 dwarn:0 dfail:0 fail:0 skip:26
ro-ivb2-i7-3770 total:102 pass:46 dwarn:33 dfail:0 fail:0 skip:22
ro-skl-i7-6700hq total:204 pass:172 dwarn:11 dfail:0 fail:0 skip:21
ro-snb-i7-2620M total:102 pass:72 dwarn:0 dfail:0 fail:0 skip:29
fi-bsw-n3050 failed to connect after reboot
fi-byt-n2820 failed to connect after reboot
ro-bdw-i7-5557U failed to connect after reboot
ro-bdw-i7-5600u failed to connect after reboot
Results at /archive/results/CI_IGT_test/RO_Patchwork_1053/
031f2bb drm-intel-nightly: 2016y-05m-30d-17h-51m-33s UTC integration manifest
8832bc7 drm/i915: fix BSM_MASK definition
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
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2016-05-30 10:32 drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? David Binderman
2016-05-30 12:54 ` [PATCH] drm/i915: fix BSM_MASK definition Jani Nikula
2016-05-30 14:15 ` drivers/gpu/drm/i915/i915_reg.h:90:shift-overflow problem ? Chris Wilson
2016-05-30 14:51 ` Jani Nikula
2016-05-31 9:56 ` ✗ Ro.CI.BAT: failure for drm/i915: fix BSM_MASK definition Patchwork
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